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authorNilay Vaish <nilay@cs.wisc.edu>2014-04-01 11:17:46 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2014-04-01 11:17:46 -0500
commitd6542d7758d52625bfb92d007d98b8f845dd69ee (patch)
tree08bfe0652b07a965e4e1b48e1bb3824a8239d38d /configs
parentb884fcf412f43ae8e1d365f23846f0f8e912ef1a (diff)
downloadgem5-d6542d7758d52625bfb92d007d98b8f845dd69ee.tar.xz
configs: use SimpleMemory when using ruby in se mode
A recent changeset altered the default memory class to DRAMCtrl. In se mode, ruby uses the physical memory to check if a given address is within the bounds of the physical memory. SimpleMemory is enough for this. Moreover, SimpleMemory does not check whether it is connected or not, something which DRAMCtrl does.
Diffstat (limited to 'configs')
-rw-r--r--configs/example/se.py9
1 files changed, 5 insertions, 4 deletions
diff --git a/configs/example/se.py b/configs/example/se.py
index 92a950319..c6b98ec0e 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -157,8 +157,6 @@ else:
(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
CPUClass.numThreads = numThreads
-MemClass = Simulation.setMemClass(options)
-
# Check -- do not allow SMT with multiple CPUs
if options.smt and options.num_cpus > 1:
fatal("You cannot use SMT with multiple CPUs!")
@@ -228,8 +226,10 @@ if options.ruby:
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
sys.exit(1)
- # Set the option for physmem so that it is not allocated any space
- system.physmem = MemClass(range=AddrRange(options.mem_size),
+ # Use SimpleMemory with the null option since this memory is only used
+ # for determining which addresses are within the range of the memory.
+ # No space allocation is required.
+ system.physmem = SimpleMemory(range=AddrRange(options.mem_size),
null = True)
options.use_map = True
Ruby.create_system(options, system)
@@ -253,6 +253,7 @@ if options.ruby:
system.cpu[i].itb.walker.port = ruby_port.slave
system.cpu[i].dtb.walker.port = ruby_port.slave
else:
+ MemClass = Simulation.setMemClass(options)
system.membus = CoherentBus()
system.system_port = system.membus.slave
CacheConfig.config_cache(options, system)