diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2011-02-03 20:23:00 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-02-03 20:23:00 -0800 |
| commit | 00f24ae92c7b9aa73e12fd8160b5756e80126db2 (patch) | |
| tree | 1d149846db0efdc77c635891c6c1433d3af1817d /configs | |
| parent | 869a046e413d7cbfdda4e33eed8191004017a83f (diff) | |
| download | gem5-00f24ae92c7b9aa73e12fd8160b5756e80126db2.tar.xz | |
Config: Keep track of uncached and cached ports separately.
This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/common/CacheConfig.py | 4 | ||||
| -rw-r--r-- | configs/example/fs.py | 2 | ||||
| -rw-r--r-- | configs/splash2/run.py | 2 |
3 files changed, 4 insertions, 4 deletions
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py index c4f91fd9e..461551817 100644 --- a/configs/common/CacheConfig.py +++ b/configs/common/CacheConfig.py @@ -52,8 +52,8 @@ def config_cache(options, system): system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), L1Cache(size = '64kB')) if options.l2cache: - system.cpu[i].connectMemPorts(system.tol2bus) + system.cpu[i].connectAllPorts(system.tol2bus, system.membus) else: - system.cpu[i].connectMemPorts(system.membus) + system.cpu[i].connectAllPorts(system.membus) return system diff --git a/configs/example/fs.py b/configs/example/fs.py index e9bc9afb6..6568f4c89 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -178,7 +178,7 @@ if len(bm) == 2: elif buildEnv['TARGET_ISA'] == 'arm': drive_sys = makeLinuxArmSystem(drive_mem_mode, bm[1]) drive_sys.cpu = DriveCPUClass(cpu_id=0) - drive_sys.cpu.connectMemPorts(drive_sys.membus) + drive_sys.cpu.connectAllPorts(drive_sys.membus) if options.fastmem: drive_sys.cpu.physmem_port = drive_sys.physmem.port if options.kernel is not None: diff --git a/configs/splash2/run.py b/configs/splash2/run.py index 8d42b3ab8..200eb191d 100644 --- a/configs/splash2/run.py +++ b/configs/splash2/run.py @@ -218,7 +218,7 @@ for cpu in cpus: cpu.addPrivateSplitL1Caches(L1(size = options.l1size, assoc = 1), L1(size = options.l1size, assoc = 4)) # connect cpu level-1 caches to shared level-2 cache - cpu.connectMemPorts(system.toL2bus) + cpu.connectAllPorts(system.toL2bus, system.membus) # ---------------------- |