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authorAndreas Hansson <andreas.hansson@arm.com>2015-02-11 10:23:28 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2015-02-11 10:23:28 -0500
commit6563ec863444ecd0191d4a3f015b78b06e2906a4 (patch)
tree0b5c6c8803d3d590b5330281885cfb3ba0ec97f2 /configs
parent550c31849024a2184887df87aae39617ebfe0d6a (diff)
downloadgem5-6563ec863444ecd0191d4a3f015b78b06e2906a4.tar.xz
cpu: Tidy up the MemTest and make false sharing more obvious
The MemTest class really only tests false sharing, and as such there was a lot of old cruft that could be removed. This patch cleans up the tester, and also makes it more clear what the assumptions are. As part of this simplification the reference functional memory is also removed. The regression configs using MemTest are updated to reflect the changes, and the stats will be bumped in a separate patch. The example config will be updated in a separate patch due to more extensive re-work. In a follow-on patch a new tester will be introduced that uses the MemChecker to implement true sharing.
Diffstat (limited to 'configs')
-rw-r--r--configs/example/memtest.py15
1 files changed, 4 insertions, 11 deletions
diff --git a/configs/example/memtest.py b/configs/example/memtest.py
index eaf3a52bd..448fa309b 100644
--- a/configs/example/memtest.py
+++ b/configs/example/memtest.py
@@ -124,7 +124,7 @@ else:
# build a list of prototypes, one for each level of treespec, starting
# at the end (last entry is tester objects)
-prototypes = [ MemTest(atomic=options.atomic, max_loads=options.maxloads,
+prototypes = [ MemTest(max_loads=options.maxloads,
percent_functional=options.functional,
percent_uncacheable=options.uncacheable,
progress_interval=options.progress) ]
@@ -146,12 +146,9 @@ for scale in treespec[:-2]:
prototypes.insert(0, next)
# system simulated
-system = System(funcmem = SimpleMemory(in_addr_map = False),
- funcbus = NoncoherentXBar(),
- physmem = SimpleMemory(latency = "100ns"),
+system = System(physmem = SimpleMemory(latency = "100ns"),
cache_line_size = block_size)
-
system.voltage_domain = VoltageDomain(voltage = '1V')
system.clk_domain = SrcClockDomain(clock = options.sys_clock,
@@ -182,14 +179,10 @@ def make_level(spec, prototypes, attach_obj, attach_port):
# we just built the MemTest objects
parent.cpu = objs
for t in objs:
- t.test = getattr(attach_obj, attach_port)
- t.functional = system.funcbus.slave
+ t.port = getattr(attach_obj, attach_port)
make_level(treespec, prototypes, system.physmem, "port")
-# connect reference memory to funcbus
-system.funcbus.master = system.funcmem.port
-
# -----------------------
# run simulation
# -----------------------
@@ -202,7 +195,7 @@ else:
# The system port is never used in the tester so merely connect it
# to avoid problems
-root.system.system_port = root.system.funcbus.slave
+root.system.system_port = root.system.physmem.cpu_side_bus.slave
# Not much point in this being higher than the L1 latency
m5.ticks.setGlobalFrequency('1ns')