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| author | Joel Hestness <hestness@cs.wisc.edu> | 2012-09-12 21:41:37 -0500 |
|---|---|---|
| committer | Joel Hestness <hestness@cs.wisc.edu> | 2012-09-12 21:41:37 -0500 |
| commit | 234fa4cf7ecd16350c1095830d26f94b2bfd3eb9 (patch) | |
| tree | b9e29dccf07623bd982d6042fa852c9b99f5390b /configs | |
| parent | 16dcb723c11afb91cc3428294bd3106425114949 (diff) | |
| download | gem5-234fa4cf7ecd16350c1095830d26f94b2bfd3eb9.tar.xz | |
Standard Switch: Drain the system before switching CPUs
When switching from an atomic CPU to any of the timing CPUs, a drain is
unnecessary since no events are scheduled in atomic mode. However, when
trying to switch CPUs starting with a timing CPU, there may be events
scheduled. This change ensures that all events are drained from the system
by calling m5.drain before switching CPUs.
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/common/Simulation.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index 8e62bcbb6..967f39b75 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -453,6 +453,7 @@ def run(options, root, testsys, cpu_class): # manually. You DON'T need to resume after just switching # CPUs if you haven't changed anything on the system level. + m5.doDrain(testsys) m5.changeToTiming(testsys) m5.switchCpus(switch_cpu_list) m5.resume(testsys) @@ -469,7 +470,7 @@ def run(options, root, testsys, cpu_class): print "Switching CPUS @ tick %s" % (m5.curTick()) print "Simulation ends instruction count:%d" % \ (testsys.switch_cpus_1[0].max_insts_any_thread) - m5.drain(testsys) + m5.doDrain(testsys) m5.switchCpus(switch_cpu_list1) m5.resume(testsys) |