diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-02-23 19:16:16 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-02-23 19:16:16 -0600 |
| commit | 7e27860ef4e5016f5a3c907fbe4c7858f83c8100 (patch) | |
| tree | 24dddb6be57a6e5e959e91fc79eeac6a5c576703 /configs | |
| parent | 5755fff99811a334874026c465ccebb9b0627230 (diff) | |
| download | gem5-7e27860ef4e5016f5a3c907fbe4c7858f83c8100.tar.xz | |
ruby: route all packets through ruby port
Currently, the interrupt controller in x86 is connected to the io bus
directly. Therefore the packets between the io devices and the interrupt
controller do not go through ruby. This patch changes ruby port so that
these packets arrive at the ruby port first, which then routes them to their
destination. Note that the patch does not make these packets go through the
ruby network. That would happen in a subsequent patch.
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/example/ruby_fs.py | 9 | ||||
| -rw-r--r-- | configs/ruby/MESI_Two_Level.py | 4 |
2 files changed, 9 insertions, 4 deletions
diff --git a/configs/example/ruby_fs.py b/configs/example/ruby_fs.py index 3c3986bdd..cd45ee8af 100644 --- a/configs/example/ruby_fs.py +++ b/configs/example/ruby_fs.py @@ -122,14 +122,17 @@ for (i, cpu) in enumerate(system.cpu): cpu.clk_domain = system.cpu_clk_domain cpu.createThreads() cpu.createInterruptController() + cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave + if buildEnv['TARGET_ISA'] == "x86": cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave - cpu.interrupts.pio = system.piobus.master - cpu.interrupts.int_master = system.piobus.slave - cpu.interrupts.int_slave = system.piobus.master + + cpu.interrupts.pio = system.ruby._cpu_ruby_ports[i].master + cpu.interrupts.int_master = system.ruby._cpu_ruby_ports[i].slave + cpu.interrupts.int_slave = system.ruby._cpu_ruby_ports[i].master system.ruby._cpu_ruby_ports[i].access_phys_mem = True diff --git a/configs/ruby/MESI_Two_Level.py b/configs/ruby/MESI_Two_Level.py index f7341f359..518336168 100644 --- a/configs/ruby/MESI_Two_Level.py +++ b/configs/ruby/MESI_Two_Level.py @@ -106,7 +106,9 @@ def create_system(options, system, piobus, dma_ports, ruby_system): l1_cntrl.sequencer = cpu_seq if piobus != None: - cpu_seq.pio_port = piobus.slave + cpu_seq.pio_master_port = piobus.slave + cpu_seq.mem_master_port = piobus.slave + cpu_seq.pio_slave_port = piobus.master exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) |