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| author | Ali Saidi <saidi@eecs.umich.edu> | 2006-12-06 14:29:10 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2006-12-06 14:29:10 -0500 |
| commit | ecbb8debf672ee1463115319a24384eeb6b98ee3 (patch) | |
| tree | dc42fa3886ff50fd9786858987e9cbd6c7b23f1b /configs | |
| parent | 4d57cab49a3012e812a054517317e95734ea8678 (diff) | |
| download | gem5-ecbb8debf672ee1463115319a24384eeb6b98ee3.tar.xz | |
Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts
getting touched.
configs/common/FSConfig.py:
Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs
src/arch/isa_parser.py:
we should readmiscregwitheffect not readmiscreg
src/arch/sparc/asi.cc:
Fix AsiIsNucleus spelling with respect to header file
Add ASI_LSU_CONTROL_REG to AsiSiMmu
src/arch/sparc/asi.hh:
Fix spelling of two ASIs
src/arch/sparc/isa/decoder.isa:
switch back to defaults letting the isa_parser insert readMiscRegWithEffect
src/arch/sparc/isa/formats/mem/util.isa:
Flesh out priviledgedString with hypervisor checks
Make load alternate set the flags correctly
src/arch/sparc/miscregfile.cc:
insert some forgotten break statements
src/arch/sparc/miscregfile.hh:
Add some comments to make it easier to find which misc register is which number
src/arch/sparc/tlb.cc:
flesh out the tlb memory mapped registers a lot more
src/base/traceflags.py:
add an IPR traceflag
src/mem/request.hh:
Fix a bad assert() in request
--HG--
extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/common/FSConfig.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index eb74346c8..72742775f 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -89,7 +89,7 @@ def makeSparcSystem(mem_mode, mdesc = None): self.bridge = Bridge() self.t1000 = T1000() self.t1000.attachIO(self.iobus) - self.physmem = PhysicalMemory(range = AddrRange('64MB'), zero = True) + self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) self.bridge.side_a = self.iobus.port self.bridge.side_b = self.membus.port |