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authorAndreas Hansson <andreas.hansson@arm.com>2015-07-03 10:14:43 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2015-07-03 10:14:43 -0400
commitb93c912013cd7f5417b92eaa33010af70e97f8ec (patch)
treee381afa1a581e3d676e9c91d9999c490fa6b1a23 /configs
parent71856cfbbcac94997839ac7831b3ac4b2ddf29a2 (diff)
downloadgem5-b93c912013cd7f5417b92eaa33010af70e97f8ec.tar.xz
mem: Remove redundant is_top_level cache parameter
This patch takes the final step in removing the is_top_level parameter from the cache. With the recent changes to read requests and write invalidations, the parameter is no longer needed, and consequently removed. This also means that asymmetric cache hierarchies are now fully supported (and we are actually using them already with L1 caches, but no table-walker caches, connected to a shared L2).
Diffstat (limited to 'configs')
-rw-r--r--configs/common/Caches.py3
-rw-r--r--configs/common/O3_ARM_v7a.py3
-rw-r--r--configs/example/memcheck.py3
-rw-r--r--configs/example/memtest.py3
4 files changed, 2 insertions, 10 deletions
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 2bdffc6c7..cfb873b5e 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -52,7 +52,6 @@ class L1Cache(BaseCache):
response_latency = 2
mshrs = 4
tgts_per_mshr = 20
- is_top_level = True
class L1_ICache(L1Cache):
is_read_only = True
@@ -76,7 +75,6 @@ class IOCache(BaseCache):
size = '1kB'
tgts_per_mshr = 12
forward_snoops = False
- is_top_level = True
class PageTableWalkerCache(BaseCache):
assoc = 2
@@ -86,7 +84,6 @@ class PageTableWalkerCache(BaseCache):
size = '1kB'
tgts_per_mshr = 12
forward_snoops = False
- is_top_level = True
# the x86 table walker actually writes to the table-walker cache
if buildEnv['TARGET_ISA'] == 'x86':
is_read_only = False
diff --git a/configs/common/O3_ARM_v7a.py b/configs/common/O3_ARM_v7a.py
index b4b66df9c..dbfdf6c41 100644
--- a/configs/common/O3_ARM_v7a.py
+++ b/configs/common/O3_ARM_v7a.py
@@ -149,7 +149,6 @@ class O3_ARM_v7a_ICache(BaseCache):
tgts_per_mshr = 8
size = '32kB'
assoc = 2
- is_top_level = True
forward_snoops = False
is_read_only = True
@@ -162,7 +161,6 @@ class O3_ARM_v7a_DCache(BaseCache):
size = '32kB'
assoc = 2
write_buffers = 16
- is_top_level = True
# TLB Cache
# Use a cache as a L2 TLB
@@ -174,7 +172,6 @@ class O3_ARM_v7aWalkCache(BaseCache):
size = '1kB'
assoc = 8
write_buffers = 16
- is_top_level = True
forward_snoops = False
is_read_only = True
diff --git a/configs/example/memcheck.py b/configs/example/memcheck.py
index f0bc26e32..ca2659ed0 100644
--- a/configs/example/memcheck.py
+++ b/configs/example/memcheck.py
@@ -154,7 +154,7 @@ for t, m in zip(testerspec, multiplier):
# Define a prototype L1 cache that we scale for all successive levels
proto_l1 = BaseCache(size = '32kB', assoc = 4,
hit_latency = 1, response_latency = 1,
- tgts_per_mshr = 8, is_top_level = True)
+ tgts_per_mshr = 8)
if options.blocking:
proto_l1.mshrs = 1
@@ -179,7 +179,6 @@ for scale in cachespec[:-1]:
next.response_latency = prev.response_latency * 10
next.assoc = prev.assoc * scale
next.mshrs = prev.mshrs * scale
- next.is_top_level = False
cache_proto.insert(0, next)
# Create a config to be used by all the traffic generators
diff --git a/configs/example/memtest.py b/configs/example/memtest.py
index 0df9f766f..a51bd2796 100644
--- a/configs/example/memtest.py
+++ b/configs/example/memtest.py
@@ -177,7 +177,7 @@ else:
# Define a prototype L1 cache that we scale for all successive levels
proto_l1 = BaseCache(size = '32kB', assoc = 4,
hit_latency = 1, response_latency = 1,
- tgts_per_mshr = 8, is_top_level = True)
+ tgts_per_mshr = 8)
if options.blocking:
proto_l1.mshrs = 1
@@ -197,7 +197,6 @@ for scale in cachespec[:-1]:
next.response_latency = prev.response_latency * 10
next.assoc = prev.assoc * scale
next.mshrs = prev.mshrs * scale
- next.is_top_level = False
cache_proto.insert(0, next)
# Make a prototype for the tester to be used throughout