diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-05 03:22:27 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-05 03:22:27 -0400 |
| commit | 554ddc7c074b0d9793a6c4972e1c449a57b94590 (patch) | |
| tree | fe8018900a41e7b35332154a12f477ca5928aa4c /configs | |
| parent | 14e5b2ea552f05e7a83970af09ed255eb26ab134 (diff) | |
| download | gem5-554ddc7c074b0d9793a6c4972e1c449a57b94590.tar.xz | |
arch, cpu: Do not forward snoops to table walker
This patch simplifies the overall CPU by changing the TLB caches such
that they do not forward snoops to the table walker port(s). Note that
only ARM and X86 are affected.
There is no reason for the ports to snoop as they do not actually take
any action, and from a performance point of view we are better of not
snooping more than we have to.
Should it at a later point be required to snoop for a particular TLB
design it is easy enough to add it back.
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/common/Caches.py | 1 | ||||
| -rw-r--r-- | configs/common/O3_ARM_v7a.py | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/configs/common/Caches.py b/configs/common/Caches.py index 9f7ac7a85..6687a967c 100644 --- a/configs/common/Caches.py +++ b/configs/common/Caches.py @@ -79,4 +79,5 @@ class PageTableWalkerCache(BaseCache): mshrs = 10 size = '1kB' tgts_per_mshr = 12 + forward_snoops = False is_top_level = True diff --git a/configs/common/O3_ARM_v7a.py b/configs/common/O3_ARM_v7a.py index 1bb2b4a5e..c291525ea 100644 --- a/configs/common/O3_ARM_v7a.py +++ b/configs/common/O3_ARM_v7a.py @@ -174,7 +174,7 @@ class O3_ARM_v7aWalkCache(BaseCache): assoc = 8 write_buffers = 16 is_top_level = True - + forward_snoops = False # L2 Cache class O3_ARM_v7aL2(BaseCache): |