Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working

after merge from head. Checkpointing may need some work now. Endian-happiness still not complete.

SConscript:
    add all devices back into make file
base/inet.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/pktfifo.cc:
dev/pktfifo.hh:
    rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system
configs/test/fs.py:
    add nics to fs.py
cpu/cpu_exec_context.cc:
    remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the
    static virtual ports in the exec context
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
    use new methods for accessing packet data
dev/ide_disk.cc:
    add some more dprintfs
dev/io_device.cc:
    delete packets when we are done with them. Update for new packet methods to access data
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart8250.cc:
dev/uart8250.hh:
mem/physical.cc:
mem/port.cc:
    dUpdate for new packet methods to access data
dev/ns_gige.cc:
    Update for new memory system
dev/ns_gige.hh:
python/m5/objects/Ethernet.py:
    update for new memory system
dev/sinic.cc:
dev/sinic.hh:
    Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions
mem/packet.hh:
    Add methods to access data instead of accessing it directly.

--HG--
extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e

2 files changed, 95 insertions, 6 deletions

diff --git a/configs/test/SysPaths.py b/configs/test/SysPaths.py
new file mode 100644
index 000000000..7f231916c
--- /dev/null
+++ b/configs/test/SysPaths.py
@@ -0,0 +1,32 @@
+from m5 import *
+
+import os.path
+import sys
+
+# Edit the following list to include the possible paths to the binary
+# and disk image directories.  The first directory on the list that
+# exists will be selected.
+SYSTEMDIR_PATH = ['/n/poolfs/z/dist/m5/system']
+
+SYSTEMDIR = None
+for d in SYSTEMDIR_PATH:
+    if os.path.exists(d):
+        SYSTEMDIR = d
+        break
+
+if not SYSTEMDIR:
+    print >>sys.stderr, "Can't find a path to system files."
+    sys.exit(1)
+
+BINDIR = SYSTEMDIR + '/binaries'
+DISKDIR = SYSTEMDIR + '/disks'
+
+def disk(file):
+    return '%s/%s' % (DISKDIR, file)
+
+def binary(file):
+    return '%s/%s' % (BINDIR, file)
+
+def script(file):
+    return '%s/%s' % ('/z/saidi/work/m5.newmem/configs/boot', file)
+
diff --git a/configs/test/fs.py b/configs/test/fs.py
index 6608aafa7..6cd4185ed 100644
--- a/configs/test/fs.py
+++ b/configs/test/fs.py
@@ -30,6 +30,44 @@ class IdeControllerPciData(PciConfigData):
     BAR3Size = '4B'
     BAR4Size = '16B'
 
+class SinicPciData(PciConfigData):
+    VendorID = 0x1291
+    DeviceID = 0x1293
+    Status = 0x0290
+    SubClassCode = 0x00
+    ClassCode = 0x02
+    ProgIF = 0x00
+    BAR0 = 0x00000000
+    BAR1 = 0x00000000
+    BAR2 = 0x00000000
+    BAR3 = 0x00000000
+    BAR4 = 0x00000000
+    BAR5 = 0x00000000
+    MaximumLatency = 0x34
+    MinimumGrant = 0xb0
+    InterruptLine = 0x1e
+    InterruptPin = 0x01
+    BAR0Size = '64kB'
+
+class NSGigEPciData(PciConfigData):
+    VendorID = 0x100B
+    DeviceID = 0x0022
+    Status = 0x0290
+    SubClassCode = 0x00
+    ClassCode = 0x02
+    ProgIF = 0x00
+    BAR0 = 0x00000001
+    BAR1 = 0x00000000
+    BAR2 = 0x00000000
+    BAR3 = 0x00000000
+    BAR4 = 0x00000000
+    BAR5 = 0x00000000
+    MaximumLatency = 0x34
+    MinimumGrant = 0xb0
+    InterruptLine = 0x1e
+    InterruptPin = 0x01
+    BAR0Size = '256B'
+    BAR1Size = '4kB'
 
 class LinuxRootDisk(IdeDisk):
     raw_image = RawDiskImage(image_file=linux_image, read_only=True)
@@ -77,9 +115,12 @@ class BaseTsunami(Tsunami):
     fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
     io = TsunamiIO(pio_addr=0x801fc000000)
     uart = Uart8250(pio_addr=0x801fc0003f8)
-#    ethernet = NSGigE(configdata=NSGigEPciData(),
+    ethernet = NSGigE(configdata=NSGigEPciData(),
+                      pci_bus=0, pci_dev=1, pci_func=0)
+    etherint = NSGigEInt(device=Parent.ethernet)
+#    ethernet = Sinic(configdata=SinicPciData(),
 #                      pci_bus=0, pci_dev=1, pci_func=0)
-#    etherint = NSGigEInt(device=Parent.ethernet)
+#    etherint = SinicInt(device=Parent.ethernet)
     console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk)
 #    bridge = PciFake(configdata=BridgePciData(), pci_bus=0, pci_dev=2, pci_func=0)
 
@@ -106,6 +147,8 @@ class LinuxAlphaSystem(LinuxAlphaSystem):
     c3 = Connector(side_a=Parent.tsunami.pchip, side_a_name='pio', side_b=Parent.magicbus)
     c4 = Connector(side_a=Parent.tsunami.pciconfig, side_a_name='pio', side_b=Parent.magicbus)
     c5 = Connector(side_a=Parent.tsunami.fake_sm_chip, side_a_name='pio', side_b=Parent.magicbus)
+    c6 = Connector(side_a=Parent.tsunami.ethernet, side_a_name='pio', side_b=Parent.magicbus)
+    c6a = Connector(side_a=Parent.tsunami.ethernet, side_a_name='dma', side_b=Parent.magicbus)
     c7 = Connector(side_a=Parent.tsunami.fake_uart1, side_a_name='pio', side_b=Parent.magicbus)
     c8 = Connector(side_a=Parent.tsunami.fake_uart2, side_a_name='pio', side_b=Parent.magicbus)
     c9 = Connector(side_a=Parent.tsunami.fake_uart3, side_a_name='pio', side_b=Parent.magicbus)
@@ -136,19 +179,33 @@ class LinuxAlphaSystem(LinuxAlphaSystem):
     intrctrl = IntrControl()
     cpu = SimpleCPU(mem=Parent.magicbus)
     sim_console = SimConsole(listener=ConsoleListener(port=3456))
-    kernel = binary('vmlinux')
+    kernel = '/z/saidi/work/m5.newmem/build/vmlinux'
     pal = binary('ts_osfpal')
     console = binary('console')
     boot_osflags = 'root=/dev/hda1 console=ttyS0'
-    readfile = os.path.join(test_base, 'halt.sh')
+#    readfile = os.path.join(test_base, 'halt.sh')
 
 
 BaseCPU.itb = AlphaITB()
 BaseCPU.dtb = AlphaDTB()
 BaseCPU.system = Parent.any
 
-class TsunamiRoot(Root):
+class TsunamiRoot(System):
     pass
 
 
-root = TsunamiRoot(clock = '2GHz', system = LinuxAlphaSystem())
+def DualRoot(ClientSystem, ServerSystem):
+    self = Root()
+    self.client = ClientSystem()
+    self.server = ServerSystem()
+
+    self.etherdump = EtherDump(file='ethertrace')
+    self.etherlink = EtherLink(int1 = Parent.client.tsunami.etherint[0],
+                               int2 = Parent.server.tsunami.etherint[0],
+                               dump = Parent.etherdump)
+    self.clock = '5GHz'
+    return self
+
+root = DualRoot(ClientSystem = LinuxAlphaSystem(readfile=script('netperf-stream-nt-client.rcS')),
+                ServerSystem = LinuxAlphaSystem(readfile=script('netperf-server.rcS')))
+