summaryrefslogtreecommitdiff
path: root/configs
diff options
context:
space:
mode:
authorAnthony Gutierrez <atgutier@umich.edu>2014-06-30 13:50:01 -0400
committerAnthony Gutierrez <atgutier@umich.edu>2014-06-30 13:50:01 -0400
commitdb267da8221ce4905e08e84967096d7a9fa23ca6 (patch)
tree2271f5354bee6d7b82bbe9e6f8dc852fd2ae5cd0 /configs
parent5b08e211ab35fd6d936dafda45014c78b5e68300 (diff)
downloadgem5-db267da8221ce4905e08e84967096d7a9fa23ca6.tar.xz
arm: make the bi-mode predictor the default for O3_ARM_v7a_BP
the branch predictor used in the Cortex-A15 is a bi-mode style predictor, see: http://arm.com/files/pdf/at-exploring_the_design_of_the_cortex-a15.pdf and http://nvidia.com/docs/IO/116757/NVIDIA_Quad_a15_whitepaper_FINALv2.pdf this patch makes the bi-mode predictor the default for the ARM O3 CPU.
Diffstat (limited to 'configs')
-rw-r--r--configs/common/O3_ARM_v7a.py11
1 files changed, 4 insertions, 7 deletions
diff --git a/configs/common/O3_ARM_v7a.py b/configs/common/O3_ARM_v7a.py
index 3b7df9988..0202d19e4 100644
--- a/configs/common/O3_ARM_v7a.py
+++ b/configs/common/O3_ARM_v7a.py
@@ -42,7 +42,7 @@ class O3_ARM_v7a_Complex_Int(FUDesc):
count = 1
-# Floating point and SIMD instructions
+# Floating point and SIMD instructions
class O3_ARM_v7a_FP(FUDesc):
opList = [ OpDesc(opClass='SimdAdd', opLat=4),
OpDesc(opClass='SimdAddAcc', opLat=4),
@@ -87,12 +87,9 @@ class O3_ARM_v7a_FUP(FUPool):
FUList = [O3_ARM_v7a_Simple_Int(), O3_ARM_v7a_Complex_Int(),
O3_ARM_v7a_Load(), O3_ARM_v7a_Store(), O3_ARM_v7a_FP()]
-# Tournament Branch Predictor
+# Bi-Mode Branch Predictor
class O3_ARM_v7a_BP(BranchPredictor):
- predType = "tournament"
- localPredictorSize = 2048
- localCtrBits = 2
- localHistoryTableSize = 1024
+ predType = "bi-mode"
globalPredictorSize = 8192
globalCtrBits = 2
choicePredictorSize = 8192
@@ -167,7 +164,7 @@ class O3_ARM_v7a_DCache(BaseCache):
write_buffers = 16
is_top_level = 'true'
-# TLB Cache
+# TLB Cache
# Use a cache as a L2 TLB
class O3_ARM_v7aWalkCache(BaseCache):
hit_latency = 4