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authorAndreas Hansson <andreas.hansson@arm.com>2012-07-12 12:56:13 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-07-12 12:56:13 -0400
commitf00cba34eb8e6bf947721f72de314f4e8bd6a8f8 (patch)
tree432ab17d82d72d5042758f25066dc64558c9a7f8 /configs
parent55bfe13705a3eccdffb6846dd87df5f190b04c99 (diff)
downloadgem5-f00cba34eb8e6bf947721f72de314f4e8bd6a8f8.tar.xz
Mem: Make SimpleMemory single ported
This patch changes the simple memory to have a single slave port rather than a vector port. The simple memory makes no attempts at modelling the contention between multiple ports, and any such multiplexing and demultiplexing could be done in a bus (or crossbar) outside the memory controller. This scenario also matches with the ongoing work on a SimpleDRAM model, which will be a single-ported single-channel controller that can be used in conjunction with a bus (or crossbar) to create a multi-port multi-channel controller. There are only very few regressions that make use of the vector port, and these are all for functional accesses only. To facilitate these cases, memtest and memtest-ruby have been updated to also have a "functional" bus to perform the (de)multiplexing of the functional memory accesses.
Diffstat (limited to 'configs')
-rw-r--r--configs/example/memtest.py6
-rw-r--r--configs/example/ruby_mem_test.py8
2 files changed, 11 insertions, 3 deletions
diff --git a/configs/example/memtest.py b/configs/example/memtest.py
index 590378920..4f57ef063 100644
--- a/configs/example/memtest.py
+++ b/configs/example/memtest.py
@@ -141,6 +141,7 @@ for scale in treespec[:-2]:
# system simulated
system = System(funcmem = SimpleMemory(in_addr_map = False),
+ funcbus = NoncoherentBus(),
physmem = SimpleMemory(latency = "100ns"))
def make_level(spec, prototypes, attach_obj, attach_port):
@@ -169,10 +170,13 @@ def make_level(spec, prototypes, attach_obj, attach_port):
parent.cpu = objs
for t in objs:
t.test = getattr(attach_obj, attach_port)
- t.functional = system.funcmem.port
+ t.functional = system.funcbus.slave
make_level(treespec, prototypes, system.physmem, "port")
+# connect reference memory to funcbus
+system.funcbus.master = system.funcmem.port
+
# -----------------------
# run simulation
# -----------------------
diff --git a/configs/example/ruby_mem_test.py b/configs/example/ruby_mem_test.py
index e3dab955c..858d13ee8 100644
--- a/configs/example/ruby_mem_test.py
+++ b/configs/example/ruby_mem_test.py
@@ -107,6 +107,7 @@ cpus = [ MemTest(atomic = False,
system = System(cpu = cpus,
funcmem = SimpleMemory(in_addr_map = False),
+ funcbus = NoncoherentBus(),
physmem = SimpleMemory())
if options.num_dmas > 0:
@@ -141,7 +142,7 @@ for (i, cpu) in enumerate(cpus):
# Tie the cpu memtester ports to the correct system ports
#
cpu.test = system.ruby._cpu_ruby_ports[i].slave
- cpu.functional = system.funcmem.port
+ cpu.functional = system.funcbus.slave
#
# Since the memtester is incredibly bursty, increase the deadlock
@@ -160,7 +161,10 @@ for (i, dma) in enumerate(dmas):
# Tie the dma memtester ports to the correct functional port
# Note that the test port has already been connected to the dma_sequencer
#
- dma.functional = system.funcmem.port
+ dma.functional = system.funcbus.slave
+
+# connect reference memory to funcbus
+system.funcbus.master = system.funcmem.port
# -----------------------
# run simulation