learning-gem5: memory access example for simple object

Change-Id: I63a68239ac73b2bce3dea5692deac29a3467d27b

1 files changed, 74 insertions, 0 deletions

diff --git a/configs/learning_gem5/part2/simple_object_memory.py b/configs/learning_gem5/part2/simple_object_memory.py
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+++ b/configs/learning_gem5/part2/simple_object_memory.py
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+# -*- coding: utf-8 -*-
+# Copyright (c) 2017 Jason Lowe-Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Lowe-Power
+
+""" Simple config/run script for the HelloObject
+
+This is probably the simplest gem5 config file you can possibly create.
+It creates a Root object and one *very* simple SimObject and simulates the
+system. Since there are no events, this "simulation" should finish immediately
+
+"""
+
+from __future__ import print_function
+from __future__ import absolute_import
+
+# import the m5 (gem5) library created when gem5 is built
+import m5
+# import all of the SimObjects
+from m5.objects import *
+
+system = System()
+system.clk_domain = SrcClockDomain()
+system.clk_domain.clock = '1GHz'
+system.clk_domain.voltage_domain = VoltageDomain()
+
+system.memory = SimpleMemory(range=AddrRange('512MB'))
+
+system.membus = SystemXBar()
+system.system_port = system.membus.slave
+
+system.memory.port = system.membus.master
+
+# Create an instantiation of the simobject you created
+system.hello = SimpleObject()
+system.goodbye = SimpleObject()
+
+system.hello.mem_side = system.membus.slave
+system.goodbye.mem_side = system.membus.slave
+system.goodbye.isread = False
+
+# set up the root SimObject and start the simulation
+root = Root(full_system = False, system = system)
+
+# instantiate all of the objects we've created above
+m5.instantiate()
+
+print("Beginning simulation!")
+exit_event = m5.simulate()
+print('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()))