summaryrefslogtreecommitdiff
path: root/configs
diff options
context:
space:
mode:
authorNikos Nikoleris <nikos.nikoleris@arm.com>2019-09-12 14:36:52 +0100
committerNikos Nikoleris <nikos.nikoleris@arm.com>2019-09-30 20:36:30 +0000
commit4c4520ca00fd5ca87bba31544442cbb5e2db1df5 (patch)
tree81b599acac6737bcc52d122613f59c04165057dd /configs
parent772ca27a97239208d5eafb795c7ec92863d671ee (diff)
downloadgem5-4c4520ca00fd5ca87bba31544442cbb5e2db1df5.tar.xz
cpu: Make use of DRAMCtrl::AddrMap in the traffic generators
Use the enum defined in the memory controller rather than custom strings and int that are later converted to the DRAMCtrl::AddrMap enum. Change-Id: Ie5b19f915f9990fd2b7505d4d1b17b6fc2100f9e Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21080 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'configs')
-rw-r--r--configs/dram/low_power_sweep.py20
-rw-r--r--configs/dram/sweep.py19
2 files changed, 16 insertions, 23 deletions
diff --git a/configs/dram/low_power_sweep.py b/configs/dram/low_power_sweep.py
index dc8de01e8..b63921b62 100644
--- a/configs/dram/low_power_sweep.py
+++ b/configs/dram/low_power_sweep.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2014-2015, 2017 ARM Limited
+# Copyright (c) 2014-2015, 2017, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -78,8 +78,9 @@ parser.add_argument("--itt-list", "-t", default="1 20 100",
parser.add_argument("--rd-perc", type=int, default=100,
help = "Percentage of read commands")
-parser.add_argument("--addr-map", type=int, default=1,
- help = "0: RoCoRaBaCh; 1: RoRaBaCoCh/RoRaBaChCo")
+parser.add_argument("--addr-map",
+ choices=m5.objects.AddrMap.vals,
+ default="RoRaBaCoCh", help = "DRAM address map policy")
parser.add_argument("--idle-end", type=int, default=50000000,
help = "time in ps of an idle period at the end ")
@@ -118,14 +119,7 @@ if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl):
system.mem_ctrls[0].null = True
# Set the address mapping based on input argument
-# Default to RoRaBaCoCh
-if args.addr_map == 0:
- system.mem_ctrls[0].addr_mapping = "RoCoRaBaCh"
-elif args.addr_map == 1:
- system.mem_ctrls[0].addr_mapping = "RoRaBaCoCh"
-else:
- fatal("Did not specify a valid address map argument")
-
+system.mem_ctrls[0].addr_mapping = args.addr_map
system.mem_ctrls[0].page_policy = args.page_policy
# We create a traffic generator state for each param combination we want to
@@ -192,6 +186,8 @@ cfg_file.write("""# STATE state# period mode=DRAM
# read_percent start_addr end_addr req_size min_itt max_itt data_limit
# stride_size page_size #banks #banks_util addr_map #ranks\n""")
+addr_map = m5.objects.AddrMap.map[args.addr_map]
+
nxt_state = 0
for itt_max in itt_max_values:
for bank in bank_util_values:
@@ -200,7 +196,7 @@ for itt_max in itt_max_values:
"%d %d %d %d %d %d %d %d %d\n" %
(nxt_state, period, "DRAM", args.rd_perc, max_addr,
burst_size, itt_min, itt_max, 0, stride_size,
- page_size, nbr_banks, bank, args.addr_map,
+ page_size, nbr_banks, bank, addr_map,
args.mem_ranks))
nxt_state = nxt_state + 1
diff --git a/configs/dram/sweep.py b/configs/dram/sweep.py
index 61b316417..385708e60 100644
--- a/configs/dram/sweep.py
+++ b/configs/dram/sweep.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2014-2015, 2018 ARM Limited
+# Copyright (c) 2014-2015, 2018-2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -78,8 +78,9 @@ parser.add_option("--mode", type="choice", default="DRAM",
help = "DRAM: Random traffic; \
DRAM_ROTATE: Traffic rotating across banks and ranks")
-parser.add_option("--addr_map", type="int", default=1,
- help = "0: RoCoRaBaCh; 1: RoRaBaCoCh/RoRaBaChCo")
+parser.add_argument("--addr-map",
+ choices=m5.objects.AddrMap.vals,
+ default="RoRaBaCoCh", help = "DRAM address map policy")
(options, args) = parser.parse_args()
@@ -122,13 +123,7 @@ if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl):
system.mem_ctrls[0].null = True
# Set the address mapping based on input argument
-# Default to RoRaBaCoCh
-if options.addr_map == 0:
- system.mem_ctrls[0].addr_mapping = "RoCoRaBaCh"
-elif options.addr_map == 1:
- system.mem_ctrls[0].addr_mapping = "RoRaBaCoCh"
-else:
- fatal("Did not specify a valid address map argument")
+system.mem_ctrls[0].addr_mapping = args.addr_map
# stay in each state for 0.25 ms, long enough to warm things up, and
# short enough to avoid hitting a refresh
@@ -183,6 +178,8 @@ root.system.mem_mode = 'timing'
m5.instantiate()
+addr_map = m5.objects.AddrMap.map[args.addr_map]
+
def trace():
generator = dram_generators[options.mode](system.tgen)
for bank in range(1, nbr_banks + 1):
@@ -192,7 +189,7 @@ def trace():
0, max_addr, burst_size, int(itt), int(itt),
options.rd_perc, 0,
num_seq_pkts, page_size, nbr_banks, bank,
- options.addr_map, options.mem_ranks)
+ addr_map, options.mem_ranks)
yield system.tgen.createExit(0)
system.tgen.start(trace())