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authorGabe Black <gblack@eecs.umich.edu>2006-11-16 14:42:44 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-11-16 14:42:44 -0500
commit74654ddd1f2233ab26c95d12f0fa73b7bb0f7c90 (patch)
tree44d9fc2d4fb84d45447df0d927111b2e6e3bacff /configs
parentcd5b33b9ff4016427fa93655f4bbd9030c4f5612 (diff)
parent14ebaa1eccff4032d59147783e98e07b81b5f1ae (diff)
downloadgem5-74654ddd1f2233ab26c95d12f0fa73b7bb0f7c90.tar.xz
Merge zower.eecs.umich.edu:/home/gblack/m5/newmemmemops
into zower.eecs.umich.edu:/eecshome/m5/newmem --HG-- extra : convert_revision : 74b2352b8f088e38cd1ecf3a8233b45df0476d93
Diffstat (limited to 'configs')
-rw-r--r--configs/common/Caches.py7
-rw-r--r--configs/example/fs.py14
-rw-r--r--configs/splash2/cluster.py303
-rw-r--r--configs/splash2/run.py2
4 files changed, 324 insertions, 2 deletions
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index d86fba246..4692ef537 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -37,3 +37,10 @@ class L1Cache(BaseCache):
tgts_per_mshr = 5
protocol = CoherenceProtocol(protocol='moesi')
+class L2Cache(BaseCache):
+ assoc = 8
+ block_size = 64
+ latency = 10
+ mshrs = 20
+ tgts_per_mshr = 12
+
diff --git a/configs/example/fs.py b/configs/example/fs.py
index a9f1d579a..a70a60b97 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -47,6 +47,7 @@ config_root = os.path.dirname(config_path)
parser = optparse.OptionParser()
# Benchmark options
+parser.add_option("--l2cache", action="store_true")
parser.add_option("--dual", action="store_true",
help="Simulate two systems attached with an ethernet link")
parser.add_option("-b", "--benchmark", action="store", type="string",
@@ -93,12 +94,23 @@ else:
test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
np = options.num_cpus
+
+if options.l2cache:
+ test_sys.l2 = L2Cache(size = '2MB')
+ test_sys.tol2bus = Bus()
+ test_sys.l2.cpu_side = test_sys.tol2bus.port
+ test_sys.l2.mem_side = test_sys.membus.port
+
test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
for i in xrange(np):
if options.caches:
test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'))
- test_sys.cpu[i].connectMemPorts(test_sys.membus)
+
+ if options.l2cache:
+ test_sys.cpu[i].connectMemPorts(test_sys.tol2bus)
+ else:
+ test_sys.cpu[i].connectMemPorts(test_sys.membus)
if len(bm) == 2:
drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
diff --git a/configs/splash2/cluster.py b/configs/splash2/cluster.py
new file mode 100644
index 000000000..799b85e6c
--- /dev/null
+++ b/configs/splash2/cluster.py
@@ -0,0 +1,303 @@
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+
+# Simple test script
+#
+# "m5 test.py"
+
+import m5
+from m5.objects import *
+import os, optparse, sys
+m5.AddToPath('../common')
+
+# --------------------
+# Define Command Line Options
+# ====================
+
+parser = optparse.OptionParser()
+
+parser.add_option("-d", "--detailed", action="store_true")
+parser.add_option("-t", "--timing", action="store_true")
+parser.add_option("-m", "--maxtick", type="int")
+parser.add_option("-c", "--numclusters",
+ help="Number of clusters", type="int")
+parser.add_option("-n", "--numcpus",
+ help="Number of cpus in total", type="int")
+parser.add_option("-f", "--frequency",
+ default = "1GHz",
+ help="Frequency of each CPU")
+parser.add_option("-p", "--protocol",
+ default="moesi",
+ help="The coherence protocol to use for the L1'a (i.e. MOESI, MOSI)")
+parser.add_option("--l1size",
+ default = "32kB")
+parser.add_option("--l1latency",
+ default = 1)
+parser.add_option("--l2size",
+ default = "256kB")
+parser.add_option("--l2latency",
+ default = 10)
+parser.add_option("--rootdir",
+ help="ROot directory of Splash2",
+ default="/dist/splash2/codes/")
+parser.add_option("-b", "--benchmark",
+ help="Splash 2 benchmark to run")
+
+(options, args) = parser.parse_args()
+
+if args:
+ print "Error: script doesn't take any positional arguments"
+ sys.exit(1)
+
+# --------------------
+# Define Splash2 Benchmarks
+# ====================
+class Cholesky(LiveProcess):
+ executable = options.rootdir + '/kernels/cholesky/CHOLESKY'
+ cmd = 'CHOLESKY -p' + str(options.numcpus) + ' '\
+ + options.rootdir + '/kernels/cholesky/inputs/tk23.O'
+
+class FFT(LiveProcess):
+ executable = options.rootdir + 'kernels/fft/FFT'
+ cmd = 'FFT -p' + str(options.numcpus) + ' -m18'
+
+class LU_contig(LiveProcess):
+ executable = options.rootdir + 'kernels/lu/contiguous_blocks/LU'
+ cmd = 'LU -p' + str(options.numcpus)
+
+class LU_noncontig(LiveProcess):
+ executable = options.rootdir + 'kernels/lu/non_contiguous_blocks/LU'
+ cmd = 'LU -p' + str(options.numcpus)
+
+class Radix(LiveProcess):
+ executable = options.rootdir + 'kernels/radix/RADIX'
+ cmd = 'RADIX -n524288 -p' + str(options.numcpus)
+
+class Barnes(LiveProcess):
+ executable = options.rootdir + 'apps/barnes/BARNES'
+ cmd = 'BARNES'
+ input = options.rootdir + 'apps/barnes/input.p' + str(options.numcpus)
+
+class FMM(LiveProcess):
+ executable = options.rootdir + 'apps/fmm/FMM'
+ cmd = 'FMM'
+ input = options.rootdir + 'apps/fmm/inputs/input.2048.p' + str(options.numcpus)
+
+class Ocean_contig(LiveProcess):
+ executable = options.rootdir + 'apps/ocean/contiguous_partitions/OCEAN'
+ cmd = 'OCEAN -p' + str(options.numcpus)
+
+class Ocean_noncontig(LiveProcess):
+ executable = options.rootdir + 'apps/ocean/non_contiguous_partitions/OCEAN'
+ cmd = 'OCEAN -p' + str(options.numcpus)
+
+class Raytrace(LiveProcess):
+ executable = options.rootdir + 'apps/raytrace/RAYTRACE'
+ cmd = 'RAYTRACE -p' + str(options.numcpus) + ' ' \
+ + options.rootdir + 'apps/raytrace/inputs/teapot.env'
+
+class Water_nsquared(LiveProcess):
+ executable = options.rootdir + 'apps/water-nsquared/WATER-NSQUARED'
+ cmd = 'WATER-NSQUARED'
+ input = options.rootdir + 'apps/water-nsquared/input.p' + str(options.numcpus)
+
+class Water_spatial(LiveProcess):
+ executable = options.rootdir + 'apps/water-spatial/WATER-SPATIAL'
+ cmd = 'WATER-SPATIAL'
+ input = options.rootdir + 'apps/water-spatial/input.p' + str(options.numcpus)
+
+
+# --------------------
+# Base L1 Cache Definition
+# ====================
+
+class L1(BaseCache):
+ latency = options.l1latency
+ block_size = 64
+ mshrs = 12
+ tgts_per_mshr = 8
+ protocol = CoherenceProtocol(protocol=options.protocol)
+
+# ----------------------
+# Base L2 Cache Definition
+# ----------------------
+
+class L2(BaseCache):
+ block_size = 64
+ latency = options.l2latency
+ mshrs = 92
+ tgts_per_mshr = 16
+ write_buffers = 8
+
+# ----------------------
+# Define the clusters with their cpus
+# ----------------------
+class Cluster:
+ pass
+
+cpusPerCluster = options.numcpus/options.numclusters
+
+busFrequency = Frequency(options.frequency)
+busFrequency *= cpusPerCluster
+
+all_cpus = []
+all_l1s = []
+all_l1buses = []
+if options.timing:
+ clusters = [ Cluster() for i in xrange(options.numclusters)]
+ for j in xrange(options.numclusters):
+ clusters[j].id = j
+ for cluster in clusters:
+ cluster.clusterbus = Bus(clock=busFrequency)
+ all_l1buses += [cluster.clusterbus]
+ cluster.cpus = [TimingSimpleCPU(cpu_id = i + cluster.id,
+ clock=options.frequency)
+ for i in xrange(cpusPerCluster)]
+ all_cpus += cluster.cpus
+ cluster.l1 = L1(size=options.l1size, assoc = 4)
+ all_l1s += [cluster.l1]
+elif options.detailed:
+ clusters = [ Cluster() for i in xrange(options.numclusters)]
+ for j in xrange(options.numclusters):
+ clusters[j].id = j
+ for cluster in clusters:
+ cluster.clusterbus = Bus(clock=busFrequency)
+ all_l1buses += [cluster.clusterbus]
+ cluster.cpus = [DerivO3CPU(cpu_id = i + cluster.id,
+ clock=options.frequency)
+ for i in xrange(cpusPerCluster)]
+ all_cpus += cluster.cpus
+ cluster.l1 = L1(size=options.l1size, assoc = 4)
+ all_l1s += [cluster.l1]
+else:
+ clusters = [ Cluster() for i in xrange(options.numclusters)]
+ for j in xrange(options.numclusters):
+ clusters[j].id = j
+ for cluster in clusters:
+ cluster.clusterbus = Bus(clock=busFrequency)
+ all_l1buses += [cluster.clusterbus]
+ cluster.cpus = [AtomicSimpleCPU(cpu_id = i + cluster.id,
+ clock=options.frequency)
+ for i in xrange(cpusPerCluster)]
+ all_cpus += cluster.cpus
+ cluster.l1 = L1(size=options.l1size, assoc = 4)
+ all_l1s += [cluster.l1]
+
+# ----------------------
+# Create a system, and add system wide objects
+# ----------------------
+system = System(cpu = all_cpus, l1_ = all_l1s, l1bus_ = all_l1buses, physmem = PhysicalMemory(),
+ membus = Bus(clock = busFrequency))
+
+system.toL2bus = Bus(clock = busFrequency)
+system.l2 = L2(size = options.l2size, assoc = 8)
+
+# ----------------------
+# Connect the L2 cache and memory together
+# ----------------------
+
+system.physmem.port = system.membus.port
+system.l2.cpu_side = system.toL2bus.port
+system.l2.mem_side = system.membus.port
+
+# ----------------------
+# Connect the L2 cache and clusters together
+# ----------------------
+for cluster in clusters:
+ cluster.l1.cpu_side = cluster.clusterbus.port
+ cluster.l1.mem_side = system.toL2bus.port
+ for cpu in cluster.cpus:
+ cpu.icache_port = cluster.clusterbus.port
+ cpu.dcache_port = cluster.clusterbus.port
+ cpu.mem = cluster.l1
+
+# ----------------------
+# Define the root
+# ----------------------
+
+root = Root(system = system)
+
+# --------------------
+# Pick the correct Splash2 Benchmarks
+# ====================
+if options.benchmark == 'Cholesky':
+ root.workload = Cholesky()
+elif options.benchmark == 'FFT':
+ root.workload = FFT()
+elif options.benchmark == 'LUContig':
+ root.workload = LU_contig()
+elif options.benchmark == 'LUNoncontig':
+ root.workload = LU_noncontig()
+elif options.benchmark == 'Radix':
+ root.workload = Radix()
+elif options.benchmark == 'Barnes':
+ root.workload = Barnes()
+elif options.benchmark == 'FMM':
+ root.workload = FMM()
+elif options.benchmark == 'OceanContig':
+ root.workload = Ocean_contig()
+elif options.benchmark == 'OceanNoncontig':
+ root.workload = Ocean_noncontig()
+elif options.benchmark == 'Raytrace':
+ root.workload = Raytrace()
+elif options.benchmark == 'WaterNSquared':
+ root.workload = Water_nsquared()
+elif options.benchmark == 'WaterSpatial':
+ root.workload = Water_spatial()
+else:
+ panic("The --benchmark environment variable was set to something" \
+ +" improper.\nUse Cholesky, FFT, LUContig, LUNoncontig, Radix" \
+ +", Barnes, FMM, OceanContig,\nOceanNoncontig, Raytrace," \
+ +" WaterNSquared, or WaterSpatial\n")
+
+# --------------------
+# Assign the workload to the cpus
+# ====================
+
+for cluster in clusters:
+ for cpu in cluster.cpus:
+ cpu.workload = root.workload
+
+# ----------------------
+# Run the simulation
+# ----------------------
+
+if options.timing or options.detailed:
+ root.system.mem_mode = 'timing'
+
+# instantiate configuration
+m5.instantiate(root)
+
+# simulate until program terminates
+if options.maxtick:
+ exit_event = m5.simulate(options.maxtick)
+else:
+ exit_event = m5.simulate(m5.MaxTick)
+
+print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
+
diff --git a/configs/splash2/run.py b/configs/splash2/run.py
index 7d56cb830..b162e0cc7 100644
--- a/configs/splash2/run.py
+++ b/configs/splash2/run.py
@@ -262,7 +262,7 @@ m5.instantiate(root)
if options.maxtick:
exit_event = m5.simulate(options.maxtick)
else:
- exit_event = m5.simulate(1000000000000)
+ exit_event = m5.simulate(m5.MaxTick)
print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()