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authorJavier Bueno <javier.bueno@metempsy.com>2019-03-27 12:35:54 +0100
committerJavier Bueno Hedo <javier.bueno@metempsy.com>2019-03-27 12:49:31 +0000
commit9059aafbd3157f515d23b7ba5e89a2d1a8cfd41a (patch)
tree768a8c785fb1a37a1984f3001a01ce2141a97f73 /configs
parent78f1f4d8f9267b5345f5a34f113eabae2a2faac9 (diff)
downloadgem5-9059aafbd3157f515d23b7ba5e89a2d1a8cfd41a.tar.xz
config: Use the corresponding HPI Caches when using the HPI cpu
The HPI cpu comes with specific cache definitions, but they are ignored when using this cpu. This patch solves this in the same way it is done for the O3_ARM_v7a cpu. Change-Id: Iabf763291099d9508e3c5eac00b1e233cb38ce6b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17708 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'configs')
-rw-r--r--configs/common/CacheConfig.py9
1 files changed, 9 insertions, 0 deletions
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index 35e147356..946060768 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -67,6 +67,15 @@ def config_cache(options, system):
core.O3_ARM_v7a_DCache, core.O3_ARM_v7a_ICache, \
core.O3_ARM_v7aL2, \
core.O3_ARM_v7aWalkCache
+ elif options.cpu_type == "HPI":
+ try:
+ import cores.arm.HPI as core
+ except:
+ print("HPI is unavailable.")
+ sys.exit(1)
+
+ dcache_class, icache_class, l2_cache_class, walk_cache_class = \
+ core.HPI_DCache, core.HPI_ICache, core.HPI_L2, core.HPI_WalkCache
else:
dcache_class, icache_class, l2_cache_class, walk_cache_class = \
L1_DCache, L1_ICache, L2Cache, None