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| author | Chun-Chen TK Hsu <chunchenhsu@google.com> | 2019-07-29 23:09:35 +0800 |
|---|---|---|
| committer | Chun-Chen TK Hsu <chunchenhsu@google.com> | 2019-07-30 11:39:20 +0000 |
| commit | 9871b73329be93c5749ef45d49079072ecbd9685 (patch) | |
| tree | 29ba81a9d319a9aa184b0e006847dd0057ec08c4 /configs | |
| parent | 24fd87af28254656029df6fc4fdd995b5f392e21 (diff) | |
| download | gem5-9871b73329be93c5749ef45d49079072ecbd9685.tar.xz | |
configs, arch-arm: Check if gic has cpu_addr attribute
Add this check because Gicv3 does not have the cpu_addr attribute.
Test: Change VExpress_GEM5_V1() to VExpress_GEM5_V2() and run the
following command to boot Debian.
M5_PATH=$PWD/fs_files ./build/ARM/gem5.opt ./configs/example/arm/fs_bigLITTLE.py \
--dtb $PWD/fs_files/binaries/armv8_gem5_v2_1cpu.dtb \
--kernel $PWD/fs_files/binaries/vmlinux \
--disk $PWD/fs_files/disks/disk.img \
--cpu-type atomic --big-cpus 1 --little-cpus 0
Change-Id: I23595ae5238dc7cc915ab09300f91aa5e8c24fdc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19648
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/example/arm/devices.py | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py index c7d5a7c4d..1cacef8b4 100644 --- a/configs/example/arm/devices.py +++ b/configs/example/arm/devices.py @@ -196,7 +196,8 @@ class SimpleSystem(LinuxArmSystem): self.realview = VExpress_GEM5_V1() - self.gic_cpu_addr = self.realview.gic.cpu_addr + if hasattr(self.realview.gic, 'cpu_addr'): + self.gic_cpu_addr = self.realview.gic.cpu_addr self.flags_addr = self.realview.realview_io.pio_addr + 0x30 self.membus = MemBus() @@ -239,7 +240,8 @@ class SimpleSystem(LinuxArmSystem): self.dmabridge.master = self.membus.slave self.dmabridge.slave = self.iobus.master - self.gic_cpu_addr = self.realview.gic.cpu_addr + if hasattr(self.realview.gic, 'cpu_addr'): + self.gic_cpu_addr = self.realview.gic.cpu_addr self.realview.attachOnChipIO(self.membus, self.iobridge) self.realview.attachIO(self.iobus) self.system_port = self.membus.slave |