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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-04-03 03:50:14 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-04-03 03:50:14 -0400 |
| commit | a8e6adb0b1284e89a63bcb14fe1fdace2b89e0c8 (patch) | |
| tree | 18965c93c0c5fad292e4a4db8c181240e1a00054 /configs | |
| parent | a7859f7e4541f2750df52ec725563d378ab7ddbb (diff) | |
| download | gem5-a8e6adb0b1284e89a63bcb14fe1fdace2b89e0c8.tar.xz | |
Atomic: Remove the physmem_port and access memory directly
This patch removes the physmem_port from the Atomic CPU and instead
uses the system pointer to access the physmem when using the fastmem
option. The system already keeps track of the physmem and the valid
memory address ranges, and with this patch we merely make use of that
existing functionality. As a result of this change, the overloaded
getMasterPort in the Atomic CPU can be removed, thus unifying the CPUs.
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/example/fs.py | 10 | ||||
| -rw-r--r-- | configs/example/se.py | 6 |
2 files changed, 12 insertions, 4 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py index 4b6956b72..38571fec3 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -1,4 +1,4 @@ -# Copyright (c) 2010-2011 ARM Limited +# Copyright (c) 2010-2012 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -133,9 +133,13 @@ else: test_sys.iobridge.slave = test_sys.iobus.master test_sys.iobridge.master = test_sys.membus.slave +# Sanity check +if options.fastmem and (options.caches or options.l2cache): + fatal("You cannot use fastmem in combination with caches!") + for i in xrange(np): if options.fastmem: - test_sys.cpu[i].physmem_port = test_sys.physmem.port + test_sys.cpu[i].fastmem = True if options.checker: test_sys.cpu[i].addCheckerCpu() @@ -160,7 +164,7 @@ if len(bm) == 2: drive_sys.cpu.createInterruptController() drive_sys.cpu.connectAllPorts(drive_sys.membus) if options.fastmem: - drive_sys.cpu.physmem_port = drive_sys.physmem.port + drive_sys.cpu.fastmem = True if options.kernel is not None: drive_sys.kernel = binary(options.kernel) drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns', diff --git a/configs/example/se.py b/configs/example/se.py index a6cf1ec19..a2f8a09dc 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -155,11 +155,15 @@ system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], physmem = PhysicalMemory(range=AddrRange("512MB")), membus = Bus(), mem_mode = test_mem_mode) +# Sanity check +if options.fastmem and (options.caches or options.l2cache): + fatal("You cannot use fastmem in combination with caches!") + for i in xrange(np): system.cpu[i].workload = multiprocesses[i] if options.fastmem: - system.cpu[0].physmem_port = system.physmem.port + system.cpu[0].fastmem = True if options.checker: system.cpu[i].addCheckerCpu() |