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author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-03-02 10:31:48 -0500 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-03-02 10:31:48 -0500 |
commit | e7f442d5273bec95f3412cdc5a82742fe32f8cf3 (patch) | |
tree | 754efd78eb14fbc59700f4f275efb9a7b29930d2 /cpu/base.hh | |
parent | 0c2c7171a83f772b297016aa7382157f070b3466 (diff) | |
download | gem5-e7f442d5273bec95f3412cdc5a82742fe32f8cf3.tar.xz |
Simple program runs with sendAtomic!
Ignoring returned latency for now.
Refactored loadSections in ObjectFile hierarchy.
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.hh:
Have each section record a pointer to image data.
This allows us to move common loadSections code into ObjectFile.
base/loader/object_file.cc:
Have each section record a pointer to image data.
This allows us to move common loadSections code into ObjectFile.
Also explicitly load BSS now since we need to allocate the
translations for it in syscall emulation.
cpu/base.hh:
Don't need memPort (just pass port in to ExecContext constructor).
cpu/exec_context.cc:
cpu/exec_context.hh:
mem/port.cc:
mem/translating_port.cc:
mem/translating_port.hh:
Pass syscall emulation Port into constructor instead of
getting it from BaseCPU.
cpu/simple/cpu.cc:
Explicitly choose one of three timing models.
Statically allocate request and packet objects when possible.
Several more minor bug fixes.
Works for simple program with SIMPLE_CPU_MEM_IMMEDIATE model now.
Probably have memory leaks with SIMPLE_CPU_MEM_TIMING (if it works at all).
Pass syscall emulation Port into constructor instead of
getting it from BaseCPU.
cpu/simple/cpu.hh:
Explicitly choose one of three timing models.
Statically allocate request and packet objects when possible.
Pass syscall emulation Port into constructor instead of
getting it from BaseCPU.
mem/physical.cc:
Set packet result field.
--HG--
extra : convert_revision : 359d0ebe4b4665867f4e26e7394ec0f1d17cfc26
Diffstat (limited to 'cpu/base.hh')
-rw-r--r-- | cpu/base.hh | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/cpu/base.hh b/cpu/base.hh index 870e26a39..c0e087f42 100644 --- a/cpu/base.hh +++ b/cpu/base.hh @@ -155,14 +155,6 @@ class BaseCPU : public SimObject int number_of_threads; /** - * A pointer to the port into the memory system to be used by syscall - * emulation. This way the data being accessed via syscalls looks in - * the memory heirachy for any changes that haven't been written back - * to main memory yet. - */ - Port* memPort; - - /** * Vector of per-thread instruction-based event queues. Used for * scheduling events based on number of instructions committed by * a particular thread. |