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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-03-09 18:35:28 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-03-09 18:35:28 -0500 |
| commit | 872bbdfc33cb82bf32576db3a57d3055a04acbac (patch) | |
| tree | 837dd214bd682ac7efa515b18857bec7d4d35bef /cpu/base.hh | |
| parent | 3adb45144aca819c9796168ecde7a263169d9d4d (diff) | |
| parent | 7b283dbc090d1197593b00fd1279b92f7c2e693e (diff) | |
| download | gem5-872bbdfc33cb82bf32576db3a57d3055a04acbac.tar.xz | |
Hand merge. Stuff probably doesn't compile.
--HG--
rename : arch/alpha/isa_desc => arch/alpha/isa/main.isa
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux/process.cc
rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux/process.hh
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64/process.cc
rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64/process.hh
rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : 7d1efcedd708815d985a951f6f010fbd83dc27e8
Diffstat (limited to 'cpu/base.hh')
| -rw-r--r-- | cpu/base.hh | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/cpu/base.hh b/cpu/base.hh index c0e087f42..0866b49a7 100644 --- a/cpu/base.hh +++ b/cpu/base.hh @@ -36,9 +36,10 @@ #include "cpu/sampler/sampler.hh" #include "sim/eventq.hh" #include "sim/sim_object.hh" -#include "targetarch/isa_traits.hh" +#include "arch/isa_traits.hh" class System; +namespace Kernel { class Statistics; } class BranchPred; class ExecContext; class Port; @@ -56,7 +57,7 @@ class BaseCPU : public SimObject #if FULL_SYSTEM protected: - uint64_t interrupts[NumInterruptLevels]; + uint64_t interrupts[TheISA::NumInterruptLevels]; uint64_t intstatus; public: @@ -66,7 +67,7 @@ class BaseCPU : public SimObject bool checkInterrupts; bool check_interrupt(int int_num) const { - if (int_num > NumInterruptLevels) + if (int_num > TheISA::NumInterruptLevels) panic("int_num out of bounds\n"); return interrupts[int_num] != 0; @@ -138,6 +139,8 @@ class BaseCPU : public SimObject virtual void startup(); virtual void regStats(); + virtual void activateWhenReady(int tid) {}; + void registerExecContexts(); /// Prepare for another CPU to take over execution. When it is @@ -230,6 +233,10 @@ class BaseCPU : public SimObject public: // Number of CPU cycles simulated Stats::Scalar<> numCycles; + +#if FULL_SYSTEM + Kernel::Statistics *kernelStats; +#endif }; #endif // __CPU_BASE_HH__ |