Code update for CPU models.

arch/alpha/isa_traits.hh:
    Add in clear functions.
cpu/base.cc:
cpu/base.hh:
    Add in CPU progress event.
cpu/base_dyn_inst.hh:
    Mimic normal registers in terms of writing/reading floats.
cpu/checker/cpu.cc:
cpu/checker/cpu.hh:
cpu/checker/cpu_builder.cc:
cpu/checker/o3_cpu_builder.cc:
    Fix up stuff.
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
    Bring up to speed with newmem.
cpu/o3/alpha_cpu_builder.cc:
    Allow for progress intervals.
cpu/o3/tournament_pred.cc:
    Fix up predictor.
cpu/o3/tournament_pred.hh:
cpu/ozone/cpu.hh:
cpu/ozone/cpu_impl.hh:
cpu/simple/cpu.cc:
    Fixes.
cpu/ozone/cpu_builder.cc:
    Allow progress interval.
cpu/ozone/front_end_impl.hh:
    Comment out this message.
cpu/ozone/lw_back_end_impl.hh:
    Remove this.
python/m5/objects/BaseCPU.py:
    Add progress interval.
python/m5/objects/Root.py:
    Allow for stat reset.
sim/serialize.cc:
sim/stat_control.cc:
    Add in stats reset.

--HG--
extra : convert_revision : fdb5ac5542099173cc30c40ea93372a065534b5e

1 files changed, 18 insertions, 0 deletions

diff --git a/cpu/base.hh b/cpu/base.hh
index dd776859d..4f1578f67 100644
--- a/cpu/base.hh
+++ b/cpu/base.hh
@@ -43,6 +43,23 @@ class CheckerCPU;
 class ExecContext;
 class System;
 
+class CPUProgressEvent : public Event
+{
+  protected:
+    Tick interval;
+    Counter lastNumInst;
+    BaseCPU *cpu;
+
+  public:
+    CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu)
+        : Event(q, Event::Stat_Event_Pri), interval(ival), lastNumInst(0), cpu(_cpu)
+    { schedule(curTick + interval); }
+
+    void process();
+
+    virtual const char *description();
+};
+
 class BaseCPU : public SimObject
 {
   protected:
@@ -125,6 +142,7 @@ class BaseCPU : public SimObject
         int cpu_id;
         Tick profile;
 #endif
+        Tick progress_interval;
         BaseCPU *checker;
 
         Params();