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authorNathan Binkert <binkertn@umich.edu>2004-11-10 18:37:19 -0500
committerNathan Binkert <binkertn@umich.edu>2004-11-10 18:37:19 -0500
commit4328480b5602decbcc7239e1884324ce23eaa3ec (patch)
treecdc6f1676b0a4faba383af8a2928c49101932ac7 /cpu/base_cpu.cc
parent4524eb0b2857b78329f8dd75c84cf89b63359c57 (diff)
downloadgem5-4328480b5602decbcc7239e1884324ce23eaa3ec.tar.xz
Don't use the global check_interrupts variable. Add a per-cpu
checkInterrupts variable and use that to determine whether an interrupt can occur on a given cycle. arch/alpha/ev5.cc: XC -> CPU (and xc -> CPU) since we're really talking about a CPU here Don't use the global check_interrupts variable. Add a per-cpu checkInterrupts variable and use that to determine whether an interrupt can occur on a given cycle. --HG-- extra : convert_revision : be4c0247e5834005c60a45796a222cffd327b64e
Diffstat (limited to 'cpu/base_cpu.cc')
-rw-r--r--cpu/base_cpu.cc7
1 files changed, 4 insertions, 3 deletions
diff --git a/cpu/base_cpu.cc b/cpu/base_cpu.cc
index 7fb8b414f..e4dd744a6 100644
--- a/cpu/base_cpu.cc
+++ b/cpu/base_cpu.cc
@@ -53,8 +53,9 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg,
Counter max_loads_any_thread,
Counter max_loads_all_threads,
System *_system, Tick freq)
- : SimObject(_name), frequency(freq), deferRegistration(_def_reg),
- number_of_threads(_number_of_threads), system(_system)
+ : SimObject(_name), frequency(freq), checkInterrupts(true),
+ deferRegistration(_def_reg), number_of_threads(_number_of_threads),
+ system(_system)
#else
BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg,
Counter max_insts_any_thread,
@@ -219,7 +220,7 @@ BaseCPU::post_interrupt(int int_num, int index)
if (index < 0 || index >= sizeof(uint64_t) * 8)
panic("int_num out of bounds\n");
- AlphaISA::check_interrupts = 1;
+ checkInterrupts = true;
interrupts[int_num] |= 1 << index;
intstatus |= (ULL(1) << int_num);
}