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author | Lisa Hsu <hsul@eecs.umich.edu> | 2004-05-18 01:40:03 -0400 |
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committer | Lisa Hsu <hsul@eecs.umich.edu> | 2004-05-18 01:40:03 -0400 |
commit | a0ccdf8aba8f71c8d66c03f5c6907d0a3c2e091f (patch) | |
tree | 71de26a0139e7db042c79989ae745377d98c3d23 /cpu/base_cpu.hh | |
parent | 4d98ab1ca92c2d88d3ee13a7518acc36a6d5bf84 (diff) | |
parent | 02af86f7e813db27b12214ea377948f07f891b69 (diff) | |
download | gem5-a0ccdf8aba8f71c8d66c03f5c6907d0a3c2e091f.tar.xz |
merge m5 with linux for the event and binning lifting
--HG--
extra : convert_revision : 09d3678746c2e9a93a9982dc75d5e1ac309cb2fa
Diffstat (limited to 'cpu/base_cpu.hh')
-rw-r--r-- | cpu/base_cpu.hh | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/cpu/base_cpu.hh b/cpu/base_cpu.hh index 0041ecc99..0b4a38b0e 100644 --- a/cpu/base_cpu.hh +++ b/cpu/base_cpu.hh @@ -31,10 +31,10 @@ #include <vector> +#include "base/statistics.hh" #include "sim/eventq.hh" #include "sim/sim_object.hh" - -#include "targetarch/isa_traits.hh" // for Addr +#include "targetarch/isa_traits.hh" #ifdef FULL_SYSTEM class System; @@ -147,11 +147,27 @@ class BaseCPU : public SimObject */ virtual BranchPred *getBranchPred() { return NULL; }; + virtual Counter totalInstructions() const { return 0; } + private: static std::vector<BaseCPU *> cpuList; //!< Static global cpu list public: static int numSimulatedCPUs() { return cpuList.size(); } + static Counter numSimulatedInstructions() + { + Counter total = 0; + + int size = cpuList.size(); + for (int i = 0; i < size; ++i) + total += cpuList[i]->totalInstructions(); + + return total; + } + + public: + // Number of CPU cycles simulated + Statistics::Scalar<> numCycles; }; #endif // __BASE_CPU_HH__ |