Initial light-weight OoO CPU checkin, along with gcc-3.4 fixes.

SConscript:
    Include new files.
arch/alpha/isa_desc:
    Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them.
arch/alpha/isa_traits.hh:
    Add enum for total number of data registers.
arch/isa_parser.py:
base/traceflags.py:
    Include new light-weight OoO CPU model.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
    Changes to abstract more away from the base dyn inst class.
cpu/beta_cpu/2bit_local_pred.cc:
cpu/beta_cpu/2bit_local_pred.hh:
cpu/beta_cpu/tournament_pred.cc:
cpu/beta_cpu/tournament_pred.hh:
    Remove redundant SatCounter class.
cpu/beta_cpu/alpha_dyn_inst.cc:
cpu/beta_cpu/alpha_full_cpu.cc:
cpu/beta_cpu/alpha_full_cpu.hh:
cpu/beta_cpu/bpred_unit.cc:
cpu/beta_cpu/inst_queue.cc:
cpu/beta_cpu/mem_dep_unit.cc:
cpu/beta_cpu/ras.cc:
cpu/beta_cpu/rename_map.cc:
cpu/beta_cpu/rename_map.hh:
cpu/beta_cpu/rob.cc:
    Fix for gcc-3.4
cpu/beta_cpu/alpha_dyn_inst.hh:
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
    Fixes for gcc-3.4.
    Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
    Make params match the current params inherited from BaseCPU.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
    Fixes for gcc-3.4
cpu/beta_cpu/full_cpu.cc:
    Use new params pointer in BaseCPU.
    Fix for gcc-3.4.
cpu/beta_cpu/full_cpu.hh:
    Use new params class from BaseCPU.
cpu/beta_cpu/iew_impl.hh:
    Remove unused function.
cpu/simple_cpu/simple_cpu.cc:
    Remove unused global variable.
cpu/static_inst.hh:
    Include OoODynInst for new lightweight OoO CPU

--HG--
extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa

1 files changed, 57 insertions, 64 deletions

diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc
index 74f6b8a6c..b8424f576 100644
--- a/cpu/base_dyn_inst.cc
+++ b/cpu/base_dyn_inst.cc
@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __BASE_DYN_INST_CC__
-#define __BASE_DYN_INST_CC__
+#ifndef __CPU_BASE_DYN_INST_CC__
+#define __CPU_BASE_DYN_INST_CC__
 
 #include <iostream>
 #include <string>
@@ -43,6 +43,8 @@
 #include "cpu/base_dyn_inst.hh"
 #include "cpu/beta_cpu/alpha_impl.hh"
 #include "cpu/beta_cpu/alpha_full_cpu.hh"
+#include "cpu/ooo_cpu/ooo_impl.hh"
+#include "cpu/ooo_cpu/ooo_cpu.hh"
 
 using namespace std;
 
@@ -74,93 +76,59 @@ BaseDynInst<Impl>::BaseDynInst(MachInst machInst, Addr inst_PC,
                                FullCPU *cpu)
     : staticInst(machInst), traceData(NULL), cpu(cpu), xc(cpu->xcBase())
 {
-    DPRINTF(FullCPU, "DynInst: Creating new DynInst.\n");
+    seqNum = seq_num;
+
+    PC = inst_PC;
+    nextPC = PC + sizeof(MachInst);
+    predPC = pred_PC;
 
+    initVars();
+}
+
+template <class Impl>
+BaseDynInst<Impl>::BaseDynInst(StaticInstPtr<ISA> &_staticInst)
+    : staticInst(_staticInst), traceData(NULL)
+{
+    initVars();
+}
+
+template <class Impl>
+void
+BaseDynInst<Impl>::initVars()
+{
     effAddr = MemReq::inval_addr;
     physEffAddr = MemReq::inval_addr;
 
     readyRegs = 0;
 
-    seqNum = seq_num;
-
-//    specMemWrite = false;
-
+    completed = false;
     canIssue = false;
     issued = false;
     executed = false;
     canCommit = false;
     squashed = false;
     squashedInIQ = false;
+    eaCalcDone = false;
 
     blockingInst = false;
     recoverInst = false;
-    specMode = false;
-//    btbMissed = false;
+
     // Eventually make this a parameter.
     threadNumber = 0;
-    // Also make this a parameter.
-    specMode = true;
+
     // Also make this a parameter, or perhaps get it from xc or cpu.
     asid = 0;
 
     // Initialize the fault to be unimplemented opcode.
     fault = Unimplemented_Opcode_Fault;
 
-    PC = inst_PC;
-    nextPC = PC + sizeof(MachInst);
-    predPC = pred_PC;
-
-    // Make sure to have the renamed register entries set to the same
-    // as the normal register entries.  It will allow the IQ to work
-    // without any modifications.
-    for (int i = 0; i < staticInst->numDestRegs(); i++)
-    {
-        _destRegIdx[i] = staticInst->destRegIdx(i);
-    }
-
-    for (int i = 0; i < staticInst->numSrcRegs(); i++)
-    {
-        _srcRegIdx[i] = staticInst->srcRegIdx(i);
-        _readySrcRegIdx[i] = 0;
-    }
-
     ++instcount;
 
-//    assert(instcount < 50);
-
     DPRINTF(FullCPU, "DynInst: Instruction created.  Instcount=%i\n",
             instcount);
 }
 
 template <class Impl>
-BaseDynInst<Impl>::BaseDynInst(StaticInstPtr<ISA> &_staticInst)
-    : staticInst(_staticInst), traceData(NULL)
-{
-    effAddr = MemReq::inval_addr;
-    physEffAddr = MemReq::inval_addr;
-
-//    specMemWrite = false;
-
-    blockingInst = false;
-    recoverInst = false;
-    specMode = false;
-//    btbMissed = false;
-
-    // Make sure to have the renamed register entries set to the same
-    // as the normal register entries.  It will allow the IQ to work
-    // without any modifications.
-    for (int i = 0; i < staticInst->numDestRegs(); i++)
-    {
-        _destRegIdx[i] = staticInst->destRegIdx(i);
-    }
-
-    for (int i = 0; i < staticInst->numSrcRegs(); i++)
-    {
-        _srcRegIdx[i] = staticInst->srcRegIdx(i);
-    }
-}
-
-template <class Impl>
 BaseDynInst<Impl>::~BaseDynInst()
 {
 /*
@@ -173,14 +141,14 @@ BaseDynInst<Impl>::~BaseDynInst()
     DPRINTF(FullCPU, "DynInst: Instruction destroyed.  Instcount=%i\n",
             instcount);
 }
-
+/*
 template <class Impl>
 FunctionalMemory *
 BaseDynInst<Impl>::getMemory(void)
 {
     return xc->mem;
 }
-/*
+
 template <class Impl>
 IntReg *
 BaseDynInst<Impl>::getIntegerRegs(void)
@@ -395,10 +363,35 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
 
 #endif
 
+template <class Impl>
+bool
+BaseDynInst<Impl>::eaSrcsReady()
+{
+    // For now I am assuming that src registers 1..n-1 are the ones that the
+    // EA calc depends on.  (i.e. src reg 0 is the source of the data to be
+    // stored)
+
+//    StaticInstPtr<ISA> eaInst = staticInst->eaCompInst();
+
+    for (int i = 1; i < numSrcRegs(); ++i)
+    {
+        if (!_readySrcRegIdx[i])
+            return false;
+    }
+
+    return true;
+}
+
+// Forward declaration...
+template class BaseDynInst<AlphaSimpleImpl>;
+template class BaseDynInst<OoOImpl>;
+
+template <>
 int
 BaseDynInst<AlphaSimpleImpl>::instcount = 0;
 
-// Forward declaration...
-template BaseDynInst<AlphaSimpleImpl>;
+template <>
+int
+BaseDynInst<OoOImpl>::instcount = 0;
 
-#endif // __BASE_DYN_INST_CC__
+#endif // __CPU_BASE_DYN_INST_CC__