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authorKevin Lim <ktlim@umich.edu>2005-05-19 01:28:25 -0400
committerKevin Lim <ktlim@umich.edu>2005-05-19 01:28:25 -0400
commitc2fcac7c0dd8dff182cb262bdf35d5c67117aa42 (patch)
treefc8804bfbe1aa820c8afa446622b9ec8c658b75e /cpu/base_dyn_inst.cc
parente5721ce6777726fa54aee49be414233656bd98d1 (diff)
downloadgem5-c2fcac7c0dd8dff182cb262bdf35d5c67117aa42.tar.xz
Fix up code for initial release. The main bug that remains is properly forwarding data from stores to loads, specifically when they are of differing sizes.
cpu/base_dyn_inst.cc: Remove unused commented out code. cpu/base_dyn_inst.hh: Fix up comments. cpu/beta_cpu/2bit_local_pred.cc: Reorder code to match header file. cpu/beta_cpu/2bit_local_pred.hh: Update comments. cpu/beta_cpu/alpha_dyn_inst.hh: Remove useless comments. cpu/beta_cpu/alpha_dyn_inst_impl.hh: cpu/beta_cpu/alpha_full_cpu_impl.hh: cpu/beta_cpu/comm.hh: cpu/beta_cpu/iew_impl.hh: Remove unused commented code. cpu/beta_cpu/alpha_full_cpu.hh: Remove obsolete comment. cpu/beta_cpu/alpha_impl.hh: cpu/beta_cpu/full_cpu.hh: Alphabetize includes. cpu/beta_cpu/bpred_unit.hh: Remove unused global history code. cpu/beta_cpu/btb.hh: cpu/beta_cpu/free_list.hh: Use full path in #defines. cpu/beta_cpu/commit.hh: cpu/beta_cpu/decode.hh: Reorder functions. cpu/beta_cpu/commit_impl.hh: Remove obsolete commented code. cpu/beta_cpu/fetch.hh: Remove obsolete comments. cpu/beta_cpu/fetch_impl.hh: cpu/beta_cpu/rename_impl.hh: Remove commented code. cpu/beta_cpu/full_cpu.cc: Remove useless defines. cpu/beta_cpu/inst_queue.hh: Use full path for #defines. cpu/beta_cpu/inst_queue_impl.hh: Reorder functions to match header file. cpu/beta_cpu/mem_dep_unit.hh: Use full path name for #defines. cpu/beta_cpu/ras.hh: Use full path names for #defines. Remove mod operation. cpu/beta_cpu/regfile.hh: Remove unused commented code, fix up current comments. cpu/beta_cpu/tournament_pred.cc: cpu/beta_cpu/tournament_pred.hh: Update programming style. --HG-- extra : convert_revision : fb9d18a853f58a1108ff827e3c123d5b52a0608a
Diffstat (limited to 'cpu/base_dyn_inst.cc')
-rw-r--r--cpu/base_dyn_inst.cc29
1 files changed, 1 insertions, 28 deletions
diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc
index ecfe5a4b0..af172f5b0 100644
--- a/cpu/base_dyn_inst.cc
+++ b/cpu/base_dyn_inst.cc
@@ -63,11 +63,6 @@ typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc> my_ha
my_hash_t thishash;
#endif
-/** This may need to be specific to an implementation. */
-//int BaseDynInst<Impl>::instcount = 0;
-
-//int break_inst = -1;
-
template <class Impl>
BaseDynInst<Impl>::BaseDynInst(MachInst machInst, Addr inst_PC,
Addr pred_PC, InstSeqNum seq_num,
@@ -129,32 +124,12 @@ BaseDynInst<Impl>::initVars()
template <class Impl>
BaseDynInst<Impl>::~BaseDynInst()
{
-/*
- if (specMemWrite) {
- // Remove effects of this instruction from speculative memory
- xc->spec_mem->erase(effAddr);
- }
-*/
--instcount;
DPRINTF(FullCPU, "DynInst: Instruction destroyed. Instcount=%i\n",
instcount);
}
-/*
-template <class Impl>
-FunctionalMemory *
-BaseDynInst<Impl>::getMemory(void)
-{
- return xc->mem;
-}
template <class Impl>
-IntReg *
-BaseDynInst<Impl>::getIntegerRegs(void)
-{
- return (spec_mode ? xc->specIntRegFile : xc->regs.intRegFile);
-}
-*/
-template <class Impl>
void
BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
{
@@ -369,8 +344,6 @@ BaseDynInst<Impl>::eaSrcsReady()
// EA calc depends on. (i.e. src reg 0 is the source of the data to be
// stored)
-// StaticInstPtr<ISA> eaInst = staticInst->eaCompInst();
-
for (int i = 1; i < numSrcRegs(); ++i)
{
if (!_readySrcRegIdx[i])
@@ -380,7 +353,7 @@ BaseDynInst<Impl>::eaSrcsReady()
return true;
}
-// Forward declaration...
+// Forward declaration
template class BaseDynInst<AlphaSimpleImpl>;
template <>