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authorKevin Lim <ktlim@umich.edu>2005-05-19 01:28:25 -0400
committerKevin Lim <ktlim@umich.edu>2005-05-19 01:28:25 -0400
commitc2fcac7c0dd8dff182cb262bdf35d5c67117aa42 (patch)
treefc8804bfbe1aa820c8afa446622b9ec8c658b75e /cpu/base_dyn_inst.hh
parente5721ce6777726fa54aee49be414233656bd98d1 (diff)
downloadgem5-c2fcac7c0dd8dff182cb262bdf35d5c67117aa42.tar.xz
Fix up code for initial release. The main bug that remains is properly forwarding data from stores to loads, specifically when they are of differing sizes.
cpu/base_dyn_inst.cc: Remove unused commented out code. cpu/base_dyn_inst.hh: Fix up comments. cpu/beta_cpu/2bit_local_pred.cc: Reorder code to match header file. cpu/beta_cpu/2bit_local_pred.hh: Update comments. cpu/beta_cpu/alpha_dyn_inst.hh: Remove useless comments. cpu/beta_cpu/alpha_dyn_inst_impl.hh: cpu/beta_cpu/alpha_full_cpu_impl.hh: cpu/beta_cpu/comm.hh: cpu/beta_cpu/iew_impl.hh: Remove unused commented code. cpu/beta_cpu/alpha_full_cpu.hh: Remove obsolete comment. cpu/beta_cpu/alpha_impl.hh: cpu/beta_cpu/full_cpu.hh: Alphabetize includes. cpu/beta_cpu/bpred_unit.hh: Remove unused global history code. cpu/beta_cpu/btb.hh: cpu/beta_cpu/free_list.hh: Use full path in #defines. cpu/beta_cpu/commit.hh: cpu/beta_cpu/decode.hh: Reorder functions. cpu/beta_cpu/commit_impl.hh: Remove obsolete commented code. cpu/beta_cpu/fetch.hh: Remove obsolete comments. cpu/beta_cpu/fetch_impl.hh: cpu/beta_cpu/rename_impl.hh: Remove commented code. cpu/beta_cpu/full_cpu.cc: Remove useless defines. cpu/beta_cpu/inst_queue.hh: Use full path for #defines. cpu/beta_cpu/inst_queue_impl.hh: Reorder functions to match header file. cpu/beta_cpu/mem_dep_unit.hh: Use full path name for #defines. cpu/beta_cpu/ras.hh: Use full path names for #defines. Remove mod operation. cpu/beta_cpu/regfile.hh: Remove unused commented code, fix up current comments. cpu/beta_cpu/tournament_pred.cc: cpu/beta_cpu/tournament_pred.hh: Update programming style. --HG-- extra : convert_revision : fb9d18a853f58a1108ff827e3c123d5b52a0608a
Diffstat (limited to 'cpu/base_dyn_inst.hh')
-rw-r--r--cpu/base_dyn_inst.hh49
1 files changed, 40 insertions, 9 deletions
diff --git a/cpu/base_dyn_inst.hh b/cpu/base_dyn_inst.hh
index 509874fad..0c9b43adc 100644
--- a/cpu/base_dyn_inst.hh
+++ b/cpu/base_dyn_inst.hh
@@ -78,6 +78,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
MaxInstDestRegs = ISA::MaxInstDestRegs, //< Max dest regs
};
+ /** The static inst used by this dyn inst. */
StaticInstPtr<ISA> staticInst;
////////////////////////////////////////////
@@ -99,7 +100,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
Fault copySrcTranslate(Addr src);
Fault copy(Addr dest);
- // Probably should be private...
+ /** @todo: Consider making this private. */
public:
/** Is this instruction valid. */
bool valid;
@@ -219,6 +220,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
~BaseDynInst();
private:
+ /** Function to initialize variables in the constructors. */
void initVars();
public:
@@ -244,9 +246,9 @@ class BaseDynInst : public FastAlloc, public RefCounted
*/
bool doneTargCalc() { return false; }
- /** Returns the calculated target of the branch. */
-// Addr readCalcTarg() { return nextPC; }
-
+ /** Returns the next PC. This could be the speculative next PC if it is
+ * called prior to the actual branch target being calculated.
+ */
Addr readNextPC() { return nextPC; }
/** Set the predicted target of this current instruction. */
@@ -294,7 +296,10 @@ class BaseDynInst : public FastAlloc, public RefCounted
/** Returns the branch target address. */
Addr branchTarget() const { return staticInst->branchTarget(PC); }
+ /** Number of source registers. */
int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
+
+ /** Number of destination registers. */
int8_t numDestRegs() const { return staticInst->numDestRegs(); }
// the following are used to track physical register usage
@@ -314,8 +319,13 @@ class BaseDynInst : public FastAlloc, public RefCounted
return staticInst->srcRegIdx(i);
}
+ /** Returns the result of an integer instruction. */
uint64_t readIntResult() { return instResult.integer; }
+
+ /** Returns the result of a floating point instruction. */
float readFloatResult() { return instResult.fp; }
+
+ /** Returns the result of a floating point (double) instruction. */
double readDoubleResult() { return instResult.dbl; }
//Push to .cc file.
@@ -328,6 +338,9 @@ class BaseDynInst : public FastAlloc, public RefCounted
}
}
+ /** Marks a specific register as ready.
+ * @todo: Move this to .cc file.
+ */
void markSrcRegReady(RegIndex src_idx)
{
++readyRegs;
@@ -339,13 +352,16 @@ class BaseDynInst : public FastAlloc, public RefCounted
}
}
+ /** Returns if a source register is ready. */
bool isReadySrcRegIdx(int idx) const
{
return this->_readySrcRegIdx[idx];
}
+ /** Sets this instruction as completed. */
void setCompleted() { completed = true; }
+ /** Returns whethe or not this instruction is completed. */
bool isCompleted() const { return completed; }
/** Sets this instruction as ready to issue. */
@@ -393,20 +409,39 @@ class BaseDynInst : public FastAlloc, public RefCounted
/** Set the next PC of this instruction (its actual target). */
void setNextPC(uint64_t val) { nextPC = val; }
+ /** Returns the exec context.
+ * @todo: Remove this once the ExecContext is no longer used.
+ */
ExecContext *xcBase() { return xc; }
private:
+ /** Instruction effective address.
+ * @todo: Consider if this is necessary or not.
+ */
Addr instEffAddr;
+ /** Whether or not the effective address calculation is completed.
+ * @todo: Consider if this is necessary or not.
+ */
bool eaCalcDone;
public:
+ /** Sets the effective address. */
void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
+
+ /** Returns the effective address. */
const Addr &getEA() const { return instEffAddr; }
+
+ /** Returns whether or not the eff. addr. calculation has been completed. */
bool doneEACalc() { return eaCalcDone; }
+
+ /** Returns whether or not the eff. addr. source registers are ready. */
bool eaSrcsReady();
public:
+ /** Load queue index. */
int16_t lqIdx;
+
+ /** Store queue index. */
int16_t sqIdx;
};
@@ -439,8 +474,7 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
if (fault == No_Fault) {
fault = cpu->read(req, data, lqIdx);
- }
- else {
+ } else {
// Return a fixed value to keep simulation deterministic even
// along misspeculated paths.
data = (T)-1;
@@ -464,9 +498,6 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
traceData->setData(data);
}
-// storeSize = sizeof(T);
-// storeData = data;
-
MemReqPtr req = new MemReq(addr, xc, sizeof(T), flags);
req->asid = asid;