Initial light-weight OoO CPU checkin, along with gcc-3.4 fixes.

SConscript:
    Include new files.
arch/alpha/isa_desc:
    Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them.
arch/alpha/isa_traits.hh:
    Add enum for total number of data registers.
arch/isa_parser.py:
base/traceflags.py:
    Include new light-weight OoO CPU model.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
    Changes to abstract more away from the base dyn inst class.
cpu/beta_cpu/2bit_local_pred.cc:
cpu/beta_cpu/2bit_local_pred.hh:
cpu/beta_cpu/tournament_pred.cc:
cpu/beta_cpu/tournament_pred.hh:
    Remove redundant SatCounter class.
cpu/beta_cpu/alpha_dyn_inst.cc:
cpu/beta_cpu/alpha_full_cpu.cc:
cpu/beta_cpu/alpha_full_cpu.hh:
cpu/beta_cpu/bpred_unit.cc:
cpu/beta_cpu/inst_queue.cc:
cpu/beta_cpu/mem_dep_unit.cc:
cpu/beta_cpu/ras.cc:
cpu/beta_cpu/rename_map.cc:
cpu/beta_cpu/rename_map.hh:
cpu/beta_cpu/rob.cc:
    Fix for gcc-3.4
cpu/beta_cpu/alpha_dyn_inst.hh:
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
    Fixes for gcc-3.4.
    Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
    Make params match the current params inherited from BaseCPU.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
    Fixes for gcc-3.4
cpu/beta_cpu/full_cpu.cc:
    Use new params pointer in BaseCPU.
    Fix for gcc-3.4.
cpu/beta_cpu/full_cpu.hh:
    Use new params class from BaseCPU.
cpu/beta_cpu/iew_impl.hh:
    Remove unused function.
cpu/simple_cpu/simple_cpu.cc:
    Remove unused global variable.
cpu/static_inst.hh:
    Include OoODynInst for new lightweight OoO CPU

--HG--
extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa

1 files changed, 41 insertions, 15 deletions

diff --git a/cpu/beta_cpu/alpha_dyn_inst_impl.hh b/cpu/beta_cpu/alpha_dyn_inst_impl.hh
index 8311067db..4a3ae99d4 100644
--- a/cpu/beta_cpu/alpha_dyn_inst_impl.hh
+++ b/cpu/beta_cpu/alpha_dyn_inst_impl.hh
@@ -4,42 +4,68 @@
 template <class Impl>
 AlphaDynInst<Impl>::AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC,
                                  InstSeqNum seq_num, FullCPU *cpu)
-    : BaseDynInst<AlphaSimpleImpl>(inst, PC, Pred_PC, seq_num, cpu)
+    : BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
 {
+    // Make sure to have the renamed register entries set to the same
+    // as the normal register entries.  It will allow the IQ to work
+    // without any modifications.
+    for (int i = 0; i < this->staticInst->numDestRegs(); i++)
+    {
+        _destRegIdx[i] = this->staticInst->destRegIdx(i);
+    }
+
+    for (int i = 0; i < this->staticInst->numSrcRegs(); i++)
+    {
+        _srcRegIdx[i] = this->staticInst->srcRegIdx(i);
+        this->_readySrcRegIdx[i] = 0;
+    }
+
 }
 
 template <class Impl>
 AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst)
-    : BaseDynInst<AlphaSimpleImpl>(_staticInst)
+    : BaseDynInst<Impl>(_staticInst)
 {
+    // Make sure to have the renamed register entries set to the same
+    // as the normal register entries.  It will allow the IQ to work
+    // without any modifications.
+    for (int i = 0; i < _staticInst->numDestRegs(); i++)
+    {
+        _destRegIdx[i] = _staticInst->destRegIdx(i);
+    }
+
+    for (int i = 0; i < _staticInst->numSrcRegs(); i++)
+    {
+        _srcRegIdx[i] = _staticInst->srcRegIdx(i);
+    }
 }
 
 template <class Impl>
 uint64_t
 AlphaDynInst<Impl>::readUniq()
 {
-    return cpu->readUniq();
+    return this->cpu->readUniq();
 }
 
 template <class Impl>
 void
 AlphaDynInst<Impl>::setUniq(uint64_t val)
 {
-    cpu->setUniq(val);
+    this->cpu->setUniq(val);
 }
 
 template <class Impl>
 uint64_t
 AlphaDynInst<Impl>::readFpcr()
 {
-    return cpu->readFpcr();
+    return this->cpu->readFpcr();
 }
 
 template <class Impl>
 void
 AlphaDynInst<Impl>::setFpcr(uint64_t val)
 {
-    cpu->setFpcr(val);
+    this->cpu->setFpcr(val);
 }
 
 #ifdef FULL_SYSTEM
@@ -47,63 +73,63 @@ template <class Impl>
 uint64_t
 AlphaDynInst<Impl>::readIpr(int idx, Fault &fault)
 {
-    return cpu->readIpr(idx, fault);
+    return this->cpu->readIpr(idx, fault);
 }
 
 template <class Impl>
 Fault
 AlphaDynInst<Impl>::setIpr(int idx, uint64_t val)
 {
-    return cpu->setIpr(idx, val);
+    return this->cpu->setIpr(idx, val);
 }
 
 template <class Impl>
 Fault
 AlphaDynInst<Impl>::hwrei()
 {
-    return cpu->hwrei();
+    return this->cpu->hwrei();
 }
 
 template <class Impl>
 int
 AlphaDynInst<Impl>::readIntrFlag()
 {
-return cpu->readIntrFlag();
+return this->cpu->readIntrFlag();
 }
 
 template <class Impl>
 void
 AlphaDynInst<Impl>::setIntrFlag(int val)
 {
-    cpu->setIntrFlag(val);
+    this->cpu->setIntrFlag(val);
 }
 
 template <class Impl>
 bool
 AlphaDynInst<Impl>::inPalMode()
 {
-    return cpu->inPalMode();
+    return this->cpu->inPalMode();
 }
 
 template <class Impl>
 void
 AlphaDynInst<Impl>::trap(Fault fault)
 {
-    cpu->trap(fault);
+    this->cpu->trap(fault);
 }
 
 template <class Impl>
 bool
 AlphaDynInst<Impl>::simPalCheck(int palFunc)
 {
-    return cpu->simPalCheck(palFunc);
+    return this->cpu->simPalCheck(palFunc);
 }
 #else
 template <class Impl>
 void
 AlphaDynInst<Impl>::syscall()
 {
-    cpu->syscall();
+    this->cpu->syscall();
 }
 #endif