Initial light-weight OoO CPU checkin, along with gcc-3.4 fixes.

SConscript:
    Include new files.
arch/alpha/isa_desc:
    Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them.
arch/alpha/isa_traits.hh:
    Add enum for total number of data registers.
arch/isa_parser.py:
base/traceflags.py:
    Include new light-weight OoO CPU model.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
    Changes to abstract more away from the base dyn inst class.
cpu/beta_cpu/2bit_local_pred.cc:
cpu/beta_cpu/2bit_local_pred.hh:
cpu/beta_cpu/tournament_pred.cc:
cpu/beta_cpu/tournament_pred.hh:
    Remove redundant SatCounter class.
cpu/beta_cpu/alpha_dyn_inst.cc:
cpu/beta_cpu/alpha_full_cpu.cc:
cpu/beta_cpu/alpha_full_cpu.hh:
cpu/beta_cpu/bpred_unit.cc:
cpu/beta_cpu/inst_queue.cc:
cpu/beta_cpu/mem_dep_unit.cc:
cpu/beta_cpu/ras.cc:
cpu/beta_cpu/rename_map.cc:
cpu/beta_cpu/rename_map.hh:
cpu/beta_cpu/rob.cc:
    Fix for gcc-3.4
cpu/beta_cpu/alpha_dyn_inst.hh:
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
    Fixes for gcc-3.4.
    Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
    Make params match the current params inherited from BaseCPU.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
    Fixes for gcc-3.4
cpu/beta_cpu/full_cpu.cc:
    Use new params pointer in BaseCPU.
    Fix for gcc-3.4.
cpu/beta_cpu/full_cpu.hh:
    Use new params class from BaseCPU.
cpu/beta_cpu/iew_impl.hh:
    Remove unused function.
cpu/simple_cpu/simple_cpu.cc:
    Remove unused global variable.
cpu/static_inst.hh:
    Include OoODynInst for new lightweight OoO CPU

--HG--
extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa

1 files changed, 13 insertions, 13 deletions

diff --git a/cpu/beta_cpu/alpha_full_cpu.hh b/cpu/beta_cpu/alpha_full_cpu.hh
index 92eebc82a..3c29dd277 100644
--- a/cpu/beta_cpu/alpha_full_cpu.hh
+++ b/cpu/beta_cpu/alpha_full_cpu.hh
@@ -87,22 +87,22 @@ class AlphaFullCPU : public FullBetaCPU<Impl>
     // trying to rename source/destination registers...
     uint64_t readUniq()
     {
-        return regFile.readUniq();
+        return this->regFile.readUniq();
     }
 
     void setUniq(uint64_t val)
     {
-        regFile.setUniq(val);
+        this->regFile.setUniq(val);
     }
 
     uint64_t readFpcr()
     {
-        return regFile.readFpcr();
+        return this->regFile.readFpcr();
     }
 
     void setFpcr(uint64_t val)
     {
-        regFile.setFpcr(val);
+        this->regFile.setFpcr(val);
     }
 
 #ifdef FULL_SYSTEM
@@ -127,13 +127,13 @@ class AlphaFullCPU : public FullBetaCPU<Impl>
     // set the register.
     IntReg getSyscallArg(int i)
     {
-        return xc->regs.intRegFile[AlphaISA::ArgumentReg0 + i];
+        return this->xc->regs.intRegFile[AlphaISA::ArgumentReg0 + i];
     }
 
     // used to shift args for indirect syscall
     void setSyscallArg(int i, IntReg val)
     {
-        xc->regs.intRegFile[AlphaISA::ArgumentReg0 + i] = val;
+        this->xc->regs.intRegFile[AlphaISA::ArgumentReg0 + i] = val;
     }
 
     void setSyscallReturn(int64_t return_value)
@@ -144,12 +144,12 @@ class AlphaFullCPU : public FullBetaCPU<Impl>
         const int RegA3 = 19;	// only place this is used
         if (return_value >= 0) {
             // no error
-            xc->regs.intRegFile[RegA3] = 0;
-            xc->regs.intRegFile[AlphaISA::ReturnValueReg] = return_value;
+            this->xc->regs.intRegFile[RegA3] = 0;
+            this->xc->regs.intRegFile[AlphaISA::ReturnValueReg] = return_value;
         } else {
             // got an error, return details
-            xc->regs.intRegFile[RegA3] = (IntReg) -1;
-            xc->regs.intRegFile[AlphaISA::ReturnValueReg] = -return_value;
+            this->xc->regs.intRegFile[RegA3] = (IntReg) -1;
+            this->xc->regs.intRegFile[AlphaISA::ReturnValueReg] = -return_value;
         }
     }
 
@@ -188,7 +188,7 @@ class AlphaFullCPU : public FullBetaCPU<Impl>
 #endif
 
         Fault error;
-        error = mem->read(req, data);
+        error = this->mem->read(req, data);
         data = htoa(data);
         return error;
     }
@@ -203,7 +203,7 @@ class AlphaFullCPU : public FullBetaCPU<Impl>
 
         // If this is a store conditional, act appropriately
         if (req->flags & LOCKED) {
-            cregs = &xc->regs.miscRegs;
+            cregs = &this->xc->regs.miscRegs;
 
             if (req->flags & UNCACHEABLE) {
                 // Don't update result register (see stq_c in isa_desc)
@@ -241,7 +241,7 @@ class AlphaFullCPU : public FullBetaCPU<Impl>
 
 #endif
 
-        return mem->write(req, (T)htoa(data));
+        return this->mem->write(req, (T)htoa(data));
     }
 
 };