diff options
author | Kevin Lim <ktlim@umich.edu> | 2005-01-11 18:52:29 -0500 |
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committer | Kevin Lim <ktlim@umich.edu> | 2005-01-11 18:52:29 -0500 |
commit | 90d4436351620bd3861013333aabd152d5492df7 (patch) | |
tree | 47216913009940d2380afce1e0ecaf6f7e1c73ec /cpu/beta_cpu/alpha_full_cpu_impl.hh | |
parent | 2fb632dbda1b5db9163322541676cef52a55029f (diff) | |
download | gem5-90d4436351620bd3861013333aabd152d5492df7.tar.xz |
Slight fixes, add in commit trace flag.
base/traceflags.py:
Add new commit rate trace flag.
build/SConstruct:
Add extra option for efence.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
Use function calls instead of direct indexing (avoids confusion).
cpu/beta_cpu/commit_impl.hh:
Add commit rate trace output (might not be worthwhile in the future).
cpu/beta_cpu/decode_impl.hh:
Remove some older hacks. Fix it so that the isntruction properly sets its next
PC to the one calculated by the branch.
cpu/beta_cpu/fetch_impl.hh:
Remove old commented code.
cpu/beta_cpu/iew_impl.hh:
Add extra check to ensure that the instruction is valid.
cpu/beta_cpu/regfile.hh:
Include trace file.
--HG--
extra : convert_revision : 4ee1dc88f8a5ed9b65486c6c111a3718a8040e42
Diffstat (limited to 'cpu/beta_cpu/alpha_full_cpu_impl.hh')
-rw-r--r-- | cpu/beta_cpu/alpha_full_cpu_impl.hh | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/cpu/beta_cpu/alpha_full_cpu_impl.hh b/cpu/beta_cpu/alpha_full_cpu_impl.hh index ee8f9f33b..611a0d80d 100644 --- a/cpu/beta_cpu/alpha_full_cpu_impl.hh +++ b/cpu/beta_cpu/alpha_full_cpu_impl.hh @@ -127,7 +127,7 @@ AlphaFullCPU<Impl>::copyToXC() for (int i = 0; i < AlphaISA::NumIntRegs; ++i) { renamed_reg = renameMap.lookup(i); - xc->regs.intRegFile[i] = regFile.intRegFile[renamed_reg]; + xc->regs.intRegFile[i] = regFile.readIntReg(renamed_reg); DPRINTF(FullCPU, "FullCPU: Copying register %i, has data %lli.\n", renamed_reg, regFile.intRegFile[renamed_reg]); } @@ -136,8 +136,8 @@ AlphaFullCPU<Impl>::copyToXC() for (int i = 0; i < AlphaISA::NumFloatRegs; ++i) { renamed_reg = renameMap.lookup(i + AlphaISA::FP_Base_DepTag); - xc->regs.floatRegFile.d[i] = regFile.floatRegFile[renamed_reg].d; - xc->regs.floatRegFile.q[i] = regFile.floatRegFile[renamed_reg].q; + xc->regs.floatRegFile.d[i] = regFile.readFloatRegDouble(renamed_reg); + xc->regs.floatRegFile.q[i] = regFile.readFloatRegInt(renamed_reg); } xc->regs.miscRegs.fpcr = regFile.miscRegs.fpcr; @@ -169,15 +169,15 @@ AlphaFullCPU<Impl>::copyFromXC() renamed_reg, regFile.intRegFile[renamed_reg], xc->regs.intRegFile[i]); - regFile.intRegFile[renamed_reg] = xc->regs.intRegFile[i]; + regFile.setIntReg(renamed_reg, xc->regs.intRegFile[i]); } // Then loop through the floating point registers. for (int i = 0; i < AlphaISA::NumFloatRegs; ++i) { renamed_reg = renameMap.lookup(i + AlphaISA::FP_Base_DepTag); - regFile.floatRegFile[renamed_reg].d = xc->regs.floatRegFile.d[i]; - regFile.floatRegFile[renamed_reg].q = xc->regs.floatRegFile.q[i] ; + regFile.setFloatRegDouble(renamed_reg, xc->regs.floatRegFile.d[i]); + regFile.setFloatRegInt(renamed_reg, xc->regs.floatRegFile.q[i]); } // Then loop through the misc registers. |