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| author | Kevin Lim <ktlim@umich.edu> | 2005-01-11 19:00:16 -0500 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2005-01-11 19:00:16 -0500 |
| commit | 42f3b4ffb3fedcb70e9ff068ed7160dc6020b8c4 (patch) | |
| tree | ba3d10f448bec63df45dff3bb7f2d6fbd6dcf9c7 /cpu/beta_cpu/comm.hh | |
| parent | 202758eea20c092bb85d1886898c3816f377d288 (diff) | |
| parent | 90d4436351620bd3861013333aabd152d5492df7 (diff) | |
| download | gem5-42f3b4ffb3fedcb70e9ff068ed7160dc6020b8c4.tar.xz | |
Merge changes.
base/traceflags.py:
Merge extra new CPU flags
cpu/static_inst.hh:
Include all the execute functions in static_inst_impl.hh
--HG--
extra : convert_revision : 78eb753bf709d37400e7c2418bb35d842d7c3f63
Diffstat (limited to 'cpu/beta_cpu/comm.hh')
| -rw-r--r-- | cpu/beta_cpu/comm.hh | 145 |
1 files changed, 145 insertions, 0 deletions
diff --git a/cpu/beta_cpu/comm.hh b/cpu/beta_cpu/comm.hh new file mode 100644 index 000000000..e327a83b9 --- /dev/null +++ b/cpu/beta_cpu/comm.hh @@ -0,0 +1,145 @@ +#ifndef __COMM_HH__ +#define __COMM_HH__ + +#include <stdint.h> +#include <vector> +#include "arch/alpha/isa_traits.hh" +#include "cpu/inst_seq.hh" + +using namespace std; + +// Find better place to put this typedef. +// The impl might be the best place for this. +typedef short int PhysRegIndex; + +template<class Impl> +struct SimpleFetchSimpleDecode { + typedef typename Impl::DynInstPtr DynInstPtr; + + int size; + + DynInstPtr insts[Impl::MaxWidth + 1]; +}; + +template<class Impl> +struct SimpleDecodeSimpleRename { + typedef typename Impl::DynInstPtr DynInstPtr; + + int size; + + DynInstPtr insts[Impl::MaxWidth + 1]; +}; + +template<class Impl> +struct SimpleRenameSimpleIEW { + typedef typename Impl::DynInstPtr DynInstPtr; + + int size; + + DynInstPtr insts[Impl::MaxWidth + 1]; +}; + +template<class Impl> +struct SimpleIEWSimpleCommit { + typedef typename Impl::DynInstPtr DynInstPtr; + + int size; + + DynInstPtr insts[Impl::MaxWidth + 1]; + + bool squash; + bool branchMispredict; + bool branchTaken; + uint64_t mispredPC; + uint64_t nextPC; + unsigned globalHist; + InstSeqNum squashedSeqNum; +}; + +template<class Impl> +struct IssueStruct { + typedef typename Impl::DynInstPtr DynInstPtr; + + int size; + + DynInstPtr insts[Impl::MaxWidth + 1]; +}; + +struct TimeBufStruct { + struct decodeComm { + bool squash; + bool stall; + bool predIncorrect; + uint64_t branchAddr; + + InstSeqNum doneSeqNum; + + // Might want to package this kind of branch stuff into a single + // struct as it is used pretty frequently. + bool branchMispredict; + bool branchTaken; + uint64_t mispredPC; + uint64_t nextPC; + unsigned globalHist; + }; + + decodeComm decodeInfo; + + // Rename can't actually tell anything to squash or send a new PC back + // because it doesn't do anything along those lines. But maybe leave + // these fields in here to keep the stages mostly orthagonal. + struct renameComm { + bool squash; + bool stall; + + uint64_t nextPC; + }; + + renameComm renameInfo; + + struct iewComm { + bool stall; + + // Also eventually include skid buffer space. + unsigned freeIQEntries; + }; + + iewComm iewInfo; + + struct commitComm { + bool squash; + bool stall; + unsigned freeROBEntries; + + bool branchMispredict; + bool branchTaken; + uint64_t mispredPC; + uint64_t nextPC; + unsigned globalHist; + + // Think of better names here. + // Will need to be a variety of sizes... + // Maybe make it a vector, that way only need one object. + std::vector<PhysRegIndex> freeRegs; + + bool robSquashing; + + // Represents the instruction that has either been retired or + // squashed. Similar to having a single bus that broadcasts the + // retired or squashed sequence number. + InstSeqNum doneSeqNum; + + // Extra bits of information so that the LDSTQ only updates when it + // needs to. + bool commitIsStore; + bool commitIsLoad; + + // Communication specifically to the IQ to tell the IQ that it can + // schedule a non-speculative instruction. + InstSeqNum nonSpecSeqNum; + }; + + commitComm commitInfo; +}; + +#endif //__COMM_HH__ |