Fix up code for initial release. The main bug that remains is properly forwarding data from stores to loads, specifically when they are of differing sizes.

cpu/base_dyn_inst.cc:
    Remove unused commented out code.
cpu/base_dyn_inst.hh:
    Fix up comments.
cpu/beta_cpu/2bit_local_pred.cc:
    Reorder code to match header file.
cpu/beta_cpu/2bit_local_pred.hh:
    Update comments.
cpu/beta_cpu/alpha_dyn_inst.hh:
    Remove useless comments.
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
cpu/beta_cpu/alpha_full_cpu_impl.hh:
cpu/beta_cpu/comm.hh:
cpu/beta_cpu/iew_impl.hh:
    Remove unused commented code.
cpu/beta_cpu/alpha_full_cpu.hh:
    Remove obsolete comment.
cpu/beta_cpu/alpha_impl.hh:
cpu/beta_cpu/full_cpu.hh:
    Alphabetize includes.
cpu/beta_cpu/bpred_unit.hh:
    Remove unused global history code.
cpu/beta_cpu/btb.hh:
cpu/beta_cpu/free_list.hh:
    Use full path in #defines.
cpu/beta_cpu/commit.hh:
cpu/beta_cpu/decode.hh:
    Reorder functions.
cpu/beta_cpu/commit_impl.hh:
    Remove obsolete commented code.
cpu/beta_cpu/fetch.hh:
    Remove obsolete comments.
cpu/beta_cpu/fetch_impl.hh:
cpu/beta_cpu/rename_impl.hh:
    Remove commented code.
cpu/beta_cpu/full_cpu.cc:
    Remove useless defines.
cpu/beta_cpu/inst_queue.hh:
    Use full path for #defines.
cpu/beta_cpu/inst_queue_impl.hh:
    Reorder functions to match header file.
cpu/beta_cpu/mem_dep_unit.hh:
    Use full path name for #defines.
cpu/beta_cpu/ras.hh:
    Use full path names for #defines.  Remove mod operation.
cpu/beta_cpu/regfile.hh:
    Remove unused commented code, fix up current comments.
cpu/beta_cpu/tournament_pred.cc:
cpu/beta_cpu/tournament_pred.hh:
    Update programming style.

--HG--
extra : convert_revision : fb9d18a853f58a1108ff827e3c123d5b52a0608a

1 files changed, 0 insertions, 31 deletions

diff --git a/cpu/beta_cpu/commit_impl.hh b/cpu/beta_cpu/commit_impl.hh
index 17ede9694..de7ecf57e 100644
--- a/cpu/beta_cpu/commit_impl.hh
+++ b/cpu/beta_cpu/commit_impl.hh
@@ -1,10 +1,3 @@
-// @todo: Bug when something reaches execute, and mispredicts, but is never
-// put into the ROB because the ROB is full.  Need rename stage to predict
-// the free ROB entries better.
-
-#ifndef __COMMIT_IMPL_HH__
-#define __COMMIT_IMPL_HH__
-
 #include "base/timebuf.hh"
 #include "cpu/beta_cpu/commit.hh"
 #include "cpu/exetrace.hh"
@@ -274,13 +267,6 @@ SimpleCommit<Impl>::commitInsts()
         // time.  However, we need to avoid updating any other state
         // incorrectly if it's already been squashed.
         if (head_inst->isSquashed()) {
-            // Hack to avoid the instruction being retired (and deleted) if
-            // it hasn't been through the IEW stage yet.
-/*
-            if (!head_inst->isExecuted()) {
-                break;
-            }
-*/
 
             DPRINTF(Commit, "Commit: Retiring squashed instruction from "
                     "ROB.\n");
@@ -418,21 +404,6 @@ SimpleCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
         ++commitCommittedBranches;
     }
 
-#if 0
-    // Explicit communication back to the LDSTQ that a load has been committed
-    // and can be removed from the LDSTQ.  Stores don't need this because
-    // the LDSTQ will already have been told that a store has reached the head
-    // of the ROB.  Consider including communication if it's a store as well
-    // to keep things orthagonal.
-    if (head_inst->isMemRef()) {
-        ++commitCommittedMemRefs;
-        if (head_inst->isLoad()) {
-            toIEW->commitInfo.commitIsLoad = true;
-            ++commitCommittedLoads;
-        }
-    }
-#endif
-
     // Now that the instruction is going to be committed, finalize its
     // trace data.
     if (head_inst->traceData) {
@@ -501,5 +472,3 @@ SimpleCommit<Impl>::readCommitPC()
 {
     return rob->readHeadPC();
 }
-
-#endif // __COMMIT_IMPL_HH__