Check in of new CPU. This checkin works under non-Fullsystem mode, with no caches.

SConscript:
    Added new CPU files to build.
arch/alpha/isa_desc:
    Changed rduniq and wruniq to be nonspeculative because the uniq register is not renamed.
arch/isa_parser.py:
    Added new CPU exec method.
base/statistics.hh:
    Minor change for namespace conflict.  Probably can change back one the new CPU files are cleaned up.
base/traceflags.py:
    Added new CPU trace flags.
cpu/static_inst.hh:
    Changed static inst to use a file that defines the execute functions.

--HG--
extra : convert_revision : bd4ce34361308280168324817fc1258dd253e519

1 files changed, 32 insertions, 0 deletions

diff --git a/cpu/beta_cpu/cpu_policy.hh b/cpu/beta_cpu/cpu_policy.hh
new file mode 100644
index 000000000..676334249
--- /dev/null
+++ b/cpu/beta_cpu/cpu_policy.hh
@@ -0,0 +1,32 @@
+#ifndef __CPU_POLICY_HH__
+#define __CPU_POLICY_HH__
+
+#include "cpu/beta_cpu/fetch.hh"
+#include "cpu/beta_cpu/decode.hh"
+#include "cpu/beta_cpu/rename.hh"
+#include "cpu/beta_cpu/iew.hh"
+#include "cpu/beta_cpu/commit.hh"
+
+#include "cpu/beta_cpu/inst_queue.hh"
+#include "cpu/beta_cpu/regfile.hh"
+#include "cpu/beta_cpu/free_list.hh"
+#include "cpu/beta_cpu/rename_map.hh"
+#include "cpu/beta_cpu/rob.hh"
+
+template<class Impl>
+struct SimpleCPUPolicy
+{
+    typedef PhysRegFile<Impl> RegFile;
+    typedef SimpleFreeList FreeList;
+    typedef SimpleRenameMap RenameMap;
+    typedef ROB<Impl> ROB;
+    typedef InstructionQueue<Impl> IQ;
+
+    typedef SimpleFetch<Impl> Fetch;
+    typedef SimpleDecode<Impl> Decode;
+    typedef SimpleRename<Impl> Rename;
+    typedef SimpleIEW<Impl, IQ> IEW;
+    typedef SimpleCommit<Impl> Commit;
+};
+
+#endif //__CPU_POLICY_HH__