shuffle files around for new directory structure

--HG--
rename : cpu/base_cpu.cc => cpu/base.cc
rename : cpu/base_cpu.hh => cpu/base.hh
rename : cpu/beta_cpu/2bit_local_pred.cc => cpu/o3/2bit_local_pred.cc
rename : cpu/beta_cpu/2bit_local_pred.hh => cpu/o3/2bit_local_pred.hh
rename : cpu/beta_cpu/alpha_full_cpu.cc => cpu/o3/alpha_cpu.cc
rename : cpu/beta_cpu/alpha_full_cpu.hh => cpu/o3/alpha_cpu.hh
rename : cpu/beta_cpu/alpha_full_cpu_builder.cc => cpu/o3/alpha_cpu_builder.cc
rename : cpu/beta_cpu/alpha_full_cpu_impl.hh => cpu/o3/alpha_cpu_impl.hh
rename : cpu/beta_cpu/alpha_dyn_inst.cc => cpu/o3/alpha_dyn_inst.cc
rename : cpu/beta_cpu/alpha_dyn_inst.hh => cpu/o3/alpha_dyn_inst.hh
rename : cpu/beta_cpu/alpha_dyn_inst_impl.hh => cpu/o3/alpha_dyn_inst_impl.hh
rename : cpu/beta_cpu/alpha_impl.hh => cpu/o3/alpha_impl.hh
rename : cpu/beta_cpu/alpha_params.hh => cpu/o3/alpha_params.hh
rename : cpu/beta_cpu/bpred_unit.cc => cpu/o3/bpred_unit.cc
rename : cpu/beta_cpu/bpred_unit.hh => cpu/o3/bpred_unit.hh
rename : cpu/beta_cpu/bpred_unit_impl.hh => cpu/o3/bpred_unit_impl.hh
rename : cpu/beta_cpu/btb.cc => cpu/o3/btb.cc
rename : cpu/beta_cpu/btb.hh => cpu/o3/btb.hh
rename : cpu/beta_cpu/comm.hh => cpu/o3/comm.hh
rename : cpu/beta_cpu/commit.cc => cpu/o3/commit.cc
rename : cpu/beta_cpu/commit.hh => cpu/o3/commit.hh
rename : cpu/beta_cpu/commit_impl.hh => cpu/o3/commit_impl.hh
rename : cpu/beta_cpu/full_cpu.cc => cpu/o3/cpu.cc
rename : cpu/beta_cpu/full_cpu.hh => cpu/o3/cpu.hh
rename : cpu/beta_cpu/cpu_policy.hh => cpu/o3/cpu_policy.hh
rename : cpu/beta_cpu/decode.cc => cpu/o3/decode.cc
rename : cpu/beta_cpu/decode.hh => cpu/o3/decode.hh
rename : cpu/beta_cpu/decode_impl.hh => cpu/o3/decode_impl.hh
rename : cpu/beta_cpu/fetch.cc => cpu/o3/fetch.cc
rename : cpu/beta_cpu/fetch.hh => cpu/o3/fetch.hh
rename : cpu/beta_cpu/fetch_impl.hh => cpu/o3/fetch_impl.hh
rename : cpu/beta_cpu/free_list.cc => cpu/o3/free_list.cc
rename : cpu/beta_cpu/free_list.hh => cpu/o3/free_list.hh
rename : cpu/beta_cpu/iew.cc => cpu/o3/iew.cc
rename : cpu/beta_cpu/iew.hh => cpu/o3/iew.hh
rename : cpu/beta_cpu/iew_impl.hh => cpu/o3/iew_impl.hh
rename : cpu/beta_cpu/inst_queue.cc => cpu/o3/inst_queue.cc
rename : cpu/beta_cpu/inst_queue.hh => cpu/o3/inst_queue.hh
rename : cpu/beta_cpu/inst_queue_impl.hh => cpu/o3/inst_queue_impl.hh
rename : cpu/beta_cpu/mem_dep_unit.cc => cpu/o3/mem_dep_unit.cc
rename : cpu/beta_cpu/mem_dep_unit.hh => cpu/o3/mem_dep_unit.hh
rename : cpu/beta_cpu/mem_dep_unit_impl.hh => cpu/o3/mem_dep_unit_impl.hh
rename : cpu/beta_cpu/ras.cc => cpu/o3/ras.cc
rename : cpu/beta_cpu/ras.hh => cpu/o3/ras.hh
rename : cpu/beta_cpu/regfile.hh => cpu/o3/regfile.hh
rename : cpu/beta_cpu/rename.cc => cpu/o3/rename.cc
rename : cpu/beta_cpu/rename.hh => cpu/o3/rename.hh
rename : cpu/beta_cpu/rename_impl.hh => cpu/o3/rename_impl.hh
rename : cpu/beta_cpu/rename_map.cc => cpu/o3/rename_map.cc
rename : cpu/beta_cpu/rename_map.hh => cpu/o3/rename_map.hh
rename : cpu/beta_cpu/rob.cc => cpu/o3/rob.cc
rename : cpu/beta_cpu/rob.hh => cpu/o3/rob.hh
rename : cpu/beta_cpu/rob_impl.hh => cpu/o3/rob_impl.hh
rename : cpu/beta_cpu/sat_counter.cc => cpu/o3/sat_counter.cc
rename : cpu/beta_cpu/sat_counter.hh => cpu/o3/sat_counter.hh
rename : cpu/beta_cpu/store_set.cc => cpu/o3/store_set.cc
rename : cpu/beta_cpu/store_set.hh => cpu/o3/store_set.hh
rename : cpu/beta_cpu/tournament_pred.cc => cpu/o3/tournament_pred.cc
rename : cpu/beta_cpu/tournament_pred.hh => cpu/o3/tournament_pred.hh
rename : cpu/ooo_cpu/ooo_cpu.cc => cpu/ozone/cpu.cc
rename : cpu/ooo_cpu/ooo_cpu.hh => cpu/ozone/cpu.hh
rename : cpu/ooo_cpu/ooo_impl.hh => cpu/ozone/cpu_impl.hh
rename : cpu/ooo_cpu/ea_list.cc => cpu/ozone/ea_list.cc
rename : cpu/ooo_cpu/ea_list.hh => cpu/ozone/ea_list.hh
rename : cpu/simple_cpu/simple_cpu.cc => cpu/simple/cpu.cc
rename : cpu/simple_cpu/simple_cpu.hh => cpu/simple/cpu.hh
rename : cpu/full_cpu/smt.hh => cpu/smt.hh
rename : cpu/full_cpu/op_class.hh => encumbered/cpu/full/op_class.hh
extra : convert_revision : c4a891d8d6d3e0e9e5ea56be47d851da44d8c032

1 files changed, 0 insertions, 169 deletions

diff --git a/cpu/beta_cpu/decode.hh b/cpu/beta_cpu/decode.hh
deleted file mode 100644
index 7b89bf288..000000000
--- a/cpu/beta_cpu/decode.hh
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __CPU_BETA_CPU_SIMPLE_DECODE_HH__
-#define __CPU_BETA_CPU_SIMPLE_DECODE_HH__
-
-#include <queue>
-
-#include "base/statistics.hh"
-#include "base/timebuf.hh"
-
-template<class Impl>
-class SimpleDecode
-{
-  private:
-    // Typedefs from the Impl.
-    typedef typename Impl::ISA ISA;
-    typedef typename Impl::FullCPU FullCPU;
-    typedef typename Impl::DynInstPtr DynInstPtr;
-    typedef typename Impl::Params Params;
-    typedef typename Impl::CPUPol CPUPol;
-
-    // Typedefs from the CPU policy.
-    typedef typename CPUPol::FetchStruct FetchStruct;
-    typedef typename CPUPol::DecodeStruct DecodeStruct;
-    typedef typename CPUPol::TimeStruct TimeStruct;
-
-    // Typedefs from the ISA.
-    typedef typename ISA::Addr Addr;
-
-  public:
-    // The only time decode will become blocked is if dispatch becomes
-    // blocked, which means IQ or ROB is probably full.
-    enum Status {
-        Running,
-        Idle,
-        Squashing,
-        Blocked,
-        Unblocking
-    };
-
-  private:
-    // May eventually need statuses on a per thread basis.
-    Status _status;
-
-  public:
-    SimpleDecode(Params &params);
-
-    void regStats();
-
-    void setCPU(FullCPU *cpu_ptr);
-
-    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
-
-    void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
-
-    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
-
-    void tick();
-
-    void decode();
-
-  private:
-    inline bool fetchInstsValid();
-
-    void block();
-
-    inline void unblock();
-
-    void squash(DynInstPtr &inst);
-
-  public:
-    // Might want to make squash a friend function.
-    void squash();
-
-  private:
-    // Interfaces to objects outside of decode.
-    /** CPU interface. */
-    FullCPU *cpu;
-
-    /** Time buffer interface. */
-    TimeBuffer<TimeStruct> *timeBuffer;
-
-    /** Wire to get rename's output from backwards time buffer. */
-    typename TimeBuffer<TimeStruct>::wire fromRename;
-
-    /** Wire to get iew's information from backwards time buffer. */
-    typename TimeBuffer<TimeStruct>::wire fromIEW;
-
-    /** Wire to get commit's information from backwards time buffer. */
-    typename TimeBuffer<TimeStruct>::wire fromCommit;
-
-    /** Wire to write information heading to previous stages. */
-    // Might not be the best name as not only fetch will read it.
-    typename TimeBuffer<TimeStruct>::wire toFetch;
-
-    /** Decode instruction queue. */
-    TimeBuffer<DecodeStruct> *decodeQueue;
-
-    /** Wire used to write any information heading to rename. */
-    typename TimeBuffer<DecodeStruct>::wire toRename;
-
-    /** Fetch instruction queue interface. */
-    TimeBuffer<FetchStruct> *fetchQueue;
-
-    /** Wire to get fetch's output from fetch queue. */
-    typename TimeBuffer<FetchStruct>::wire fromFetch;
-
-    /** Skid buffer between fetch and decode. */
-    std::queue<FetchStruct> skidBuffer;
-
-    //Consider making these unsigned to avoid any confusion.
-    /** Rename to decode delay, in ticks. */
-    unsigned renameToDecodeDelay;
-
-    /** IEW to decode delay, in ticks. */
-    unsigned iewToDecodeDelay;
-
-    /** Commit to decode delay, in ticks. */
-    unsigned commitToDecodeDelay;
-
-    /** Fetch to decode delay, in ticks. */
-    unsigned fetchToDecodeDelay;
-
-    /** The width of decode, in instructions. */
-    unsigned decodeWidth;
-
-    /** The instruction that decode is currently on.  It needs to have
-     *  persistent state so that when a stall occurs in the middle of a
-     *  group of instructions, it can restart at the proper instruction.
-     */
-    unsigned numInst;
-
-    Stats::Scalar<> decodeIdleCycles;
-    Stats::Scalar<> decodeBlockedCycles;
-    Stats::Scalar<> decodeUnblockCycles;
-    Stats::Scalar<> decodeSquashCycles;
-    Stats::Scalar<> decodeBranchMispred;
-    Stats::Scalar<> decodeControlMispred;
-    Stats::Scalar<> decodeDecodedInsts;
-    Stats::Scalar<> decodeSquashedInsts;
-};
-
-#endif // __CPU_BETA_CPU_SIMPLE_DECODE_HH__