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author | Kevin Lim <ktlim@umich.edu> | 2004-08-20 14:54:07 -0400 |
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committer | Kevin Lim <ktlim@umich.edu> | 2004-08-20 14:54:07 -0400 |
commit | 04745696b6b523c5e90c335298099600d4a14a76 (patch) | |
tree | 66b578f8c44355ccf8e970fe59b52554dde9d0ce /cpu/beta_cpu/fetch.hh | |
parent | 8295a8050c1096dc560f4976724adada810e56e1 (diff) | |
download | gem5-04745696b6b523c5e90c335298099600d4a14a76.tar.xz |
Check in of new CPU. This checkin works under non-Fullsystem mode, with no caches.
SConscript:
Added new CPU files to build.
arch/alpha/isa_desc:
Changed rduniq and wruniq to be nonspeculative because the uniq register is not renamed.
arch/isa_parser.py:
Added new CPU exec method.
base/statistics.hh:
Minor change for namespace conflict. Probably can change back one the new CPU files are cleaned up.
base/traceflags.py:
Added new CPU trace flags.
cpu/static_inst.hh:
Changed static inst to use a file that defines the execute functions.
--HG--
extra : convert_revision : bd4ce34361308280168324817fc1258dd253e519
Diffstat (limited to 'cpu/beta_cpu/fetch.hh')
-rw-r--r-- | cpu/beta_cpu/fetch.hh | 160 |
1 files changed, 160 insertions, 0 deletions
diff --git a/cpu/beta_cpu/fetch.hh b/cpu/beta_cpu/fetch.hh new file mode 100644 index 000000000..5717c65ac --- /dev/null +++ b/cpu/beta_cpu/fetch.hh @@ -0,0 +1,160 @@ +// Todo: add in statistics, only get the MachInst and let decode actually +// decode, think about SMT fetch, +// fix up branch prediction stuff into one thing, +// Figure out where to advance time buffer. Add a way to get a +// stage's current status. + +#ifndef __SIMPLE_FETCH_HH__ +#define __SIMPLE_FETCH_HH__ + +//Will want to include: time buffer, structs, MemInterface, Event, +//whatever class bzero uses, MemReqPtr + +#include "base/timebuf.hh" +#include "sim/eventq.hh" +#include "cpu/pc_event.hh" +#include "cpu/beta_cpu/comm.hh" +#include "mem/mem_interface.hh" + +using namespace std; + +/** + * SimpleFetch class to fetch a single instruction each cycle. SimpleFetch + * will stall if there's an Icache miss, but otherwise assumes a one cycle + * Icache hit. This will be replaced with a more fleshed out class in the + * future. + */ + +template <class Impl> +class SimpleFetch +{ + public: + /** Typedefs from Impl. */ + typedef typename Impl::ISA ISA; + typedef typename Impl::DynInst DynInst; + typedef typename Impl::FullCPU FullCPU; + typedef typename Impl::Params Params; + + typedef typename Impl::FetchStruct FetchStruct; + typedef typename Impl::TimeStruct TimeStruct; + + /** Typedefs from ISA. */ + typedef typename ISA::MachInst MachInst; + + public: + enum Status { + Running, + Idle, + Squashing, + Blocked, + IcacheMissStall, + IcacheMissComplete + }; + + // May eventually need statuses on a per thread basis. + Status _status; + + bool stalled; + + public: + /** SimpleFetch constructor. */ + SimpleFetch(Params ¶ms); + + void setCPU(FullCPU *cpu_ptr); + + void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer); + + void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); + + void tick(); + + void fetch(); + + void processCacheCompletion(); + +// private: + // Figure out PC vs next PC and how it should be updated + void squash(Addr newPC); + + public: + class CacheCompletionEvent : public Event + { + private: + SimpleFetch *fetch; + + public: + CacheCompletionEvent(SimpleFetch *_fetch); + + virtual void process(); + virtual const char *description(); + }; + + CacheCompletionEvent cacheCompletionEvent; + + private: + /** Pointer to the FullCPU. */ + FullCPU *cpu; + + /** Time buffer interface. */ + TimeBuffer<TimeStruct> *timeBuffer; + + /** Wire to get decode's information from backwards time buffer. */ + typename TimeBuffer<TimeStruct>::wire fromDecode; + + /** Wire to get rename's information from backwards time buffer. */ + typename TimeBuffer<TimeStruct>::wire fromRename; + + /** Wire to get iew's information from backwards time buffer. */ + typename TimeBuffer<TimeStruct>::wire fromIEW; + + /** Wire to get commit's information from backwards time buffer. */ + typename TimeBuffer<TimeStruct>::wire fromCommit; + + // Will probably have this sit in the FullCPU and just pass a pointr in. + // Simplifies the constructors of all stages. + /** Internal fetch instruction queue. */ + TimeBuffer<FetchStruct> *fetchQueue; + + //Might be annoying how this name is different than the queue. + /** Wire used to write any information heading to decode. */ + typename TimeBuffer<FetchStruct>::wire toDecode; + + /** Icache interface. */ + MemInterface *icacheInterface; + + /** Memory request used to access cache. */ + MemReqPtr memReq; + + /** Decode to fetch delay, in ticks. */ + unsigned decodeToFetchDelay; + + /** Rename to fetch delay, in ticks. */ + unsigned renameToFetchDelay; + + /** IEW to fetch delay, in ticks. */ + unsigned iewToFetchDelay; + + /** Commit to fetch delay, in ticks. */ + unsigned commitToFetchDelay; + + /** The width of fetch in instructions. */ + unsigned fetchWidth; + + /** Cache block size. */ + int blkSize; + + /** Mask to get a cache block's address. */ + Addr cacheBlockMask; + + /** The instruction being fetched. */ + MachInst inst; + + /** Size of instructions. */ + int instSize; + + /** Icache stall statistics. */ +// Stats::Scalar<> icacheStallCycles; +// Counter lastIcacheStall; +}; + +#endif //__SIMPLE_FETCH_HH__ |