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author | Kevin Lim <ktlim@umich.edu> | 2005-05-03 10:56:47 -0400 |
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committer | Kevin Lim <ktlim@umich.edu> | 2005-05-03 10:56:47 -0400 |
commit | 61d95de4c886911fa0b7dc9d587ffe5b292b739e (patch) | |
tree | d70531683cfb9bdb7ab967a99fbb3d6e0c34814f /cpu/beta_cpu/fetch.hh | |
parent | 6191d3e4443b5337232a238a3a0dd5d11249e223 (diff) | |
download | gem5-61d95de4c886911fa0b7dc9d587ffe5b292b739e.tar.xz |
Large update of several parts of my code. The most notable change is the inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version.
SConscript:
arch/isa_parser.py:
cpu/base_dyn_inst.cc:
Remove OOO CPU stuff.
arch/alpha/faults.hh:
Add fake memory fault. This will be removed eventually.
arch/alpha/isa_desc:
Change EA comp and Mem accessor to be const StaticInstPtrs.
cpu/base_dyn_inst.hh:
Update read/write calls to use load queue and store queue indices.
cpu/beta_cpu/alpha_dyn_inst.hh:
Change to const StaticInst in the register accessors.
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
Update syscall code with thread numbers.
cpu/beta_cpu/alpha_full_cpu.hh:
Alter some of the full system code so it will compile without errors.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
Update some of the full system code so it compiles.
cpu/beta_cpu/alpha_params.hh:
cpu/beta_cpu/fetch_impl.hh:
Remove asid.
cpu/beta_cpu/comm.hh:
Remove global history field.
cpu/beta_cpu/commit.hh:
Comment out rename map.
cpu/beta_cpu/commit_impl.hh:
Update some of the full system code so it compiles. Also change it so that it handles memory instructions properly.
cpu/beta_cpu/cpu_policy.hh:
Removed IQ from the IEW template parameter to make it more uniform.
cpu/beta_cpu/decode.hh:
Add debug function.
cpu/beta_cpu/decode_impl.hh:
Slight updates for decode in the case where it causes a squash.
cpu/beta_cpu/fetch.hh:
cpu/beta_cpu/rob.hh:
Comment out unneccessary code.
cpu/beta_cpu/full_cpu.cc:
Changed some of the full system code so it compiles. Updated exec contexts and so forth to hopefully make multithreading easier.
cpu/beta_cpu/full_cpu.hh:
Updated some of the full system code to make it compile.
cpu/beta_cpu/iew.cc:
Removed IQ from template parameter to IEW.
cpu/beta_cpu/iew.hh:
Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue.
cpu/beta_cpu/iew_impl.hh:
New handling of memory instructions through the Load/Store queue.
cpu/beta_cpu/inst_queue.hh:
Updated comment.
cpu/beta_cpu/inst_queue_impl.hh:
Slightly different handling of memory instructions due to Load/Store queue.
cpu/beta_cpu/regfile.hh:
Updated full system code so it compiles.
cpu/beta_cpu/rob_impl.hh:
Moved some code around; no major functional changes.
cpu/ooo_cpu/ooo_cpu.hh:
Slight updates to OOO CPU; still does not work.
cpu/static_inst.hh:
Remove OOO CPU stuff. Change ea comp and mem acc to return const StaticInst.
kern/kernel_stats.hh:
Extra forward declares added due to compile error.
--HG--
extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e
Diffstat (limited to 'cpu/beta_cpu/fetch.hh')
-rw-r--r-- | cpu/beta_cpu/fetch.hh | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/cpu/beta_cpu/fetch.hh b/cpu/beta_cpu/fetch.hh index 7a3893708..da22baa9b 100644 --- a/cpu/beta_cpu/fetch.hh +++ b/cpu/beta_cpu/fetch.hh @@ -74,7 +74,6 @@ class SimpleFetch void processCacheCompletion(); -// private: // Figure out PC vs next PC and how it should be updated void squash(const Addr &new_PC); @@ -93,9 +92,6 @@ class SimpleFetch */ bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC); - // Might not want this function... -// inline void recordGlobalHist(DynInstPtr &inst); - /** * Fetches the cache line that contains fetch_PC. Returns any * fault that happened. Puts the data into the class variable @@ -184,9 +180,6 @@ class SimpleFetch /** Mask to get a cache block's address. */ Addr cacheBlkMask; - /** The instruction being fetched. */ -// MachInst inst; - /** The cache line being fetched. */ uint8_t *cacheData; |