Fix up code for initial release. The main bug that remains is properly forwarding data from stores to loads, specifically when they are of differing sizes.

cpu/base_dyn_inst.cc:
    Remove unused commented out code.
cpu/base_dyn_inst.hh:
    Fix up comments.
cpu/beta_cpu/2bit_local_pred.cc:
    Reorder code to match header file.
cpu/beta_cpu/2bit_local_pred.hh:
    Update comments.
cpu/beta_cpu/alpha_dyn_inst.hh:
    Remove useless comments.
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
cpu/beta_cpu/alpha_full_cpu_impl.hh:
cpu/beta_cpu/comm.hh:
cpu/beta_cpu/iew_impl.hh:
    Remove unused commented code.
cpu/beta_cpu/alpha_full_cpu.hh:
    Remove obsolete comment.
cpu/beta_cpu/alpha_impl.hh:
cpu/beta_cpu/full_cpu.hh:
    Alphabetize includes.
cpu/beta_cpu/bpred_unit.hh:
    Remove unused global history code.
cpu/beta_cpu/btb.hh:
cpu/beta_cpu/free_list.hh:
    Use full path in #defines.
cpu/beta_cpu/commit.hh:
cpu/beta_cpu/decode.hh:
    Reorder functions.
cpu/beta_cpu/commit_impl.hh:
    Remove obsolete commented code.
cpu/beta_cpu/fetch.hh:
    Remove obsolete comments.
cpu/beta_cpu/fetch_impl.hh:
cpu/beta_cpu/rename_impl.hh:
    Remove commented code.
cpu/beta_cpu/full_cpu.cc:
    Remove useless defines.
cpu/beta_cpu/inst_queue.hh:
    Use full path for #defines.
cpu/beta_cpu/inst_queue_impl.hh:
    Reorder functions to match header file.
cpu/beta_cpu/mem_dep_unit.hh:
    Use full path name for #defines.
cpu/beta_cpu/ras.hh:
    Use full path names for #defines.  Remove mod operation.
cpu/beta_cpu/regfile.hh:
    Remove unused commented code, fix up current comments.
cpu/beta_cpu/tournament_pred.cc:
cpu/beta_cpu/tournament_pred.hh:
    Update programming style.

--HG--
extra : convert_revision : fb9d18a853f58a1108ff827e3c123d5b52a0608a

1 files changed, 1 insertions, 3 deletions

diff --git a/cpu/beta_cpu/fetch_impl.hh b/cpu/beta_cpu/fetch_impl.hh
index 0ec4c63a3..7adfecc52 100644
--- a/cpu/beta_cpu/fetch_impl.hh
+++ b/cpu/beta_cpu/fetch_impl.hh
@@ -35,8 +35,7 @@ SimpleFetch<Impl>::CacheCompletionEvent::description()
 
 template<class Impl>
 SimpleFetch<Impl>::SimpleFetch(Params &params)
-    : //cacheCompletionEvent(this),
-      icacheInterface(params.icacheInterface),
+    : icacheInterface(params.icacheInterface),
       branchPred(params),
       decodeToFetchDelay(params.decodeToFetchDelay),
       renameToFetchDelay(params.renameToFetchDelay),
@@ -254,7 +253,6 @@ SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
         // up this stage once the cache miss completes.
         if (result != MA_HIT && icacheInterface->doEvents()) {
             memReq->completionEvent = new CacheCompletionEvent(this);
-//            lastIcacheStall = curTick;
 
             // How does current model work as far as individual
             // stages scheduling/unscheduling?