Large update of several parts of my code. The most notable change is the inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version.

SConscript:
arch/isa_parser.py:
cpu/base_dyn_inst.cc:
    Remove OOO CPU stuff.
arch/alpha/faults.hh:
    Add fake memory fault.  This will be removed eventually.
arch/alpha/isa_desc:
    Change EA comp and Mem accessor to be const StaticInstPtrs.
cpu/base_dyn_inst.hh:
    Update read/write calls to use load queue and store queue indices.
cpu/beta_cpu/alpha_dyn_inst.hh:
    Change to const StaticInst in the register accessors.
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
    Update syscall code with thread numbers.
cpu/beta_cpu/alpha_full_cpu.hh:
    Alter some of the full system code so it will compile without errors.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
    Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
    Update some of the full system code so it compiles.
cpu/beta_cpu/alpha_params.hh:
cpu/beta_cpu/fetch_impl.hh:
    Remove asid.
cpu/beta_cpu/comm.hh:
    Remove global history field.
cpu/beta_cpu/commit.hh:
    Comment out rename map.
cpu/beta_cpu/commit_impl.hh:
    Update some of the full system code so it compiles.  Also change it so that it handles memory instructions properly.
cpu/beta_cpu/cpu_policy.hh:
    Removed IQ from the IEW template parameter to make it more uniform.
cpu/beta_cpu/decode.hh:
    Add debug function.
cpu/beta_cpu/decode_impl.hh:
    Slight updates for decode in the case where it causes a squash.
cpu/beta_cpu/fetch.hh:
cpu/beta_cpu/rob.hh:
    Comment out unneccessary code.
cpu/beta_cpu/full_cpu.cc:
    Changed some of the full system code so it compiles.  Updated exec contexts and so forth to hopefully make multithreading easier.
cpu/beta_cpu/full_cpu.hh:
    Updated some of the full system code to make it compile.
cpu/beta_cpu/iew.cc:
    Removed IQ from template parameter to IEW.
cpu/beta_cpu/iew.hh:
    Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue.
cpu/beta_cpu/iew_impl.hh:
    New handling of memory instructions through the Load/Store queue.
cpu/beta_cpu/inst_queue.hh:
    Updated comment.
cpu/beta_cpu/inst_queue_impl.hh:
    Slightly different handling of memory instructions due to Load/Store queue.
cpu/beta_cpu/regfile.hh:
    Updated full system code so it compiles.
cpu/beta_cpu/rob_impl.hh:
    Moved some code around; no major functional changes.
cpu/ooo_cpu/ooo_cpu.hh:
    Slight updates to OOO CPU; still does not work.
cpu/static_inst.hh:
    Remove OOO CPU stuff.  Change ea comp and mem acc to return const StaticInst.
kern/kernel_stats.hh:
    Extra forward declares added due to compile error.

--HG--
extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e

1 files changed, 54 insertions, 30 deletions

diff --git a/cpu/beta_cpu/full_cpu.cc b/cpu/beta_cpu/full_cpu.cc
index 04c74393b..3cf5d4aaa 100644
--- a/cpu/beta_cpu/full_cpu.cc
+++ b/cpu/beta_cpu/full_cpu.cc
@@ -16,7 +16,7 @@
 using namespace std;
 
 BaseFullCPU::BaseFullCPU(Params &params)
-    : BaseCPU(&params)
+    : BaseCPU(&params), cpu_id(0)
 {
 }
 
@@ -82,15 +82,14 @@ FullBetaCPU<Impl>::FullBetaCPU(Params &params)
 
 #ifdef FULL_SYSTEM
       system(params.system),
-      memCtrl(system->memCtrl),
+      memCtrl(system->memctrl),
       physmem(system->physmem),
       itb(params.itb),
       dtb(params.dtb),
       mem(params.mem),
 #else
-      process(params.process),
-      asid(params.asid),
-      mem(process->getMemory()),
+      // Hardcoded for a single thread!!
+      mem(params.workload[0]->getMemory()),
 #endif // FULL_SYSTEM
 
       icacheInterface(params.icacheInterface),
@@ -100,20 +99,40 @@ FullBetaCPU<Impl>::FullBetaCPU(Params &params)
       funcExeInst(0)
 {
     _status = Idle;
+
+#ifndef FULL_SYSTEM
+    thread.resize(this->number_of_threads);
+#endif
+
+    for (int i = 0; i < this->number_of_threads; ++i) {
 #ifdef FULL_SYSTEM
-    xc = new ExecContext(this, 0, system, itb, dtb, mem);
+        assert(i == 0);
+        system->execContexts[i] =
+            new ExecContext(this, i, system, itb, dtb, mem);
 
-    // initialize CPU, including PC
-    TheISA::initCPU(&xc->regs);
+        // initialize CPU, including PC
+        TheISA::initCPU(&system->execContexts[i]->regs);
+        execContexts.push_back(system->execContexts[i]);
 #else
-    DPRINTF(FullCPU, "FullCPU: Process's starting PC is %#x, process is %#x",
-            process->prog_entry, process);
-    xc = new ExecContext(this, /* thread_num */ 0, process, /* asid */ 0);
-
-    assert(process->getMemory() != NULL);
-    assert(mem != NULL);
+        if (i < params.workload.size()) {
+            DPRINTF(FullCPU, "FullCPU: Workload[%i]'s starting PC is %#x, "
+                    "process is %#x",
+                    i, params.workload[i]->prog_entry, thread[i]);
+            thread[i] = new ExecContext(this, i, params.workload[i], i);
+        }
+        assert(params.workload[i]->getMemory() != NULL);
+        assert(mem != NULL);
+        execContexts.push_back(thread[i]);
 #endif // !FULL_SYSTEM
-    execContexts.push_back(xc);
+    }
+
+    // Note that this is a hack so that my code which still uses xc-> will
+    // still work.  I should remove this eventually
+#ifdef FULL_SYSTEM
+    xc = system->execContexts[0];
+#else
+    xc = thread[0];
+#endif
 
     // The stages also need their CPU pointer setup.  However this must be
     // done at the upper level CPU because they have pointers to the upper
@@ -202,29 +221,33 @@ FullBetaCPU<Impl>::init()
 
         // Need to do a copy of the xc->regs into the CPU's regfile so
         // that it can start properly.
-
+#ifdef FULL_SYSTEM
+        ExecContext *src_xc = system->execContexts[0];
+#else
+        ExecContext *src_xc = thread[0];
+#endif
         // First loop through the integer registers.
         for (int i = 0; i < Impl::ISA::NumIntRegs; ++i)
         {
-            regFile.intRegFile[i] = xc->regs.intRegFile[i];
+            regFile.intRegFile[i] = src_xc->regs.intRegFile[i];
         }
 
         // Then loop through the floating point registers.
         for (int i = 0; i < Impl::ISA::NumFloatRegs; ++i)
         {
-            regFile.floatRegFile[i].d = xc->regs.floatRegFile.d[i];
-            regFile.floatRegFile[i].q = xc->regs.floatRegFile.q[i];
+            regFile.floatRegFile[i].d = src_xc->regs.floatRegFile.d[i];
+            regFile.floatRegFile[i].q = src_xc->regs.floatRegFile.q[i];
         }
 
         // Then loop through the misc registers.
-        regFile.miscRegs.fpcr = xc->regs.miscRegs.fpcr;
-        regFile.miscRegs.uniq = xc->regs.miscRegs.uniq;
-        regFile.miscRegs.lock_flag = xc->regs.miscRegs.lock_flag;
-        regFile.miscRegs.lock_addr = xc->regs.miscRegs.lock_addr;
+        regFile.miscRegs.fpcr = src_xc->regs.miscRegs.fpcr;
+        regFile.miscRegs.uniq = src_xc->regs.miscRegs.uniq;
+        regFile.miscRegs.lock_flag = src_xc->regs.miscRegs.lock_flag;
+        regFile.miscRegs.lock_addr = src_xc->regs.miscRegs.lock_addr;
 
         // Then finally set the PC and the next PC.
-        regFile.pc = xc->regs.pc;
-        regFile.npc = xc->regs.npc;
+        regFile.pc = src_xc->regs.pc;
+        regFile.npc = src_xc->regs.npc;
     }
 }
 
@@ -277,13 +300,13 @@ FullBetaCPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
 
     // Set all status's to active, schedule the
     // CPU's tick event.
-    tickEvent.schedule(curTick);
     for (int i = 0; i < execContexts.size(); ++i) {
-        execContexts[i]->activate();
+        ExecContext *xc = execContexts[i];
+        if (xc->status() == ExecContext::Active && _status != Running) {
+            _status = Running;
+            tickEvent.schedule(curTick);
+        }
     }
-
-    // Switch out the other CPU.
-    oldCPU->switchOut();
 }
 
 template <class Impl>
@@ -463,6 +486,7 @@ FullBetaCPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num)
                 inst_to_delete->seqNum, inst_to_delete->readPC());
 
         // Remove the instruction from the list.
+        instList.back() = NULL;
         instList.pop_back();
 
         // Mark it as squashed.