Update to make multiple instruction issue and different latencies work.

Also change to ref counted DynInst.

SConscript:
    Add branch predictor, BTB, load store queue, and storesets.
arch/isa_parser.py:
    Specify the template parameter for AlphaDynInst
base/traceflags.py:
    Add load store queue, store set, and mem dependence unit to the
    list of trace flags.
cpu/base_dyn_inst.cc:
    Change formating, add in debug statement.
cpu/base_dyn_inst.hh:
    Change DynInst to be RefCounted, add flag to clear whether or not this
    instruction can commit.  This is likely to be removed in the future.
cpu/beta_cpu/alpha_dyn_inst.cc:
    AlphaDynInst has been changed to be templated, so now this CC file
    is just used to force instantiations of AlphaDynInst.
cpu/beta_cpu/alpha_dyn_inst.hh:
    Changed AlphaDynInst to be templated on Impl.  Removed some unnecessary
    functions.
cpu/beta_cpu/alpha_full_cpu.cc:
    AlphaFullCPU has been changed to be templated, so this CC file is now
    just used to force instantation of AlphaFullCPU.
cpu/beta_cpu/alpha_full_cpu.hh:
    Change AlphaFullCPU to be templated on Impl.
cpu/beta_cpu/alpha_impl.hh:
    Update it to reflect AlphaDynInst and AlphaFullCPU being templated
    on Impl.  Also removed time buffers from here, as they are really
    a part of the CPU and are thus in the CPU policy now.
cpu/beta_cpu/alpha_params.hh:
    Make AlphaSimpleParams inherit from the BaseFullCPU so that it doesn't
    need to specifically declare any parameters that are already in the
    BaseFullCPU.
cpu/beta_cpu/comm.hh:
    Changed the structure of the time buffer communication structs.  Now
    they include the size of the packet of instructions it is sending.
    Added some parameters to the backwards communication struct, mainly
    for squashing.
cpu/beta_cpu/commit.hh:
    Update typenames to reflect change in location of time buffer structs.
    Update DynInst to DynInstPtr (it is refcounted now).
cpu/beta_cpu/commit_impl.hh:
    Formatting changes mainly.  Also sends back proper information
    on branch mispredicts so that the bpred unit can update itself.
    Updated behavior for non-speculative instructions (stores, any
    other non-spec instructions): once they reach the head of the ROB,
    the ROB signals back to the IQ that it can go ahead and issue the
    non-speculative instruction.  The instruction itself is updated so that
    commit won't try to commit it again until it is done executing.
cpu/beta_cpu/cpu_policy.hh:
    Added branch prediction unit, mem dependence prediction unit, load
    store queue.  Moved time buffer structs from AlphaSimpleImpl to here.
cpu/beta_cpu/decode.hh:
    Changed typedefs to reflect change in location of time buffer structs
    and also the change from DynInst to ref counted DynInstPtr.
cpu/beta_cpu/decode_impl.hh:
    Continues to buffer instructions even while unblocking now.  Changed
    how it loops through groups of instructions so it can properly block
    during the middle of a group of instructions.
cpu/beta_cpu/fetch.hh:
    Changed typedefs to reflect change in location of time buffer structs
    and the change to ref counted DynInsts.  Also added in branch
    brediction unit.
cpu/beta_cpu/fetch_impl.hh:
    Add in branch prediction.  Changed how fetch checks inputs and its
    current state to make for easier logic.
cpu/beta_cpu/free_list.cc:
    Changed int regs and float regs to logically use one flat namespace.
    Future change will be moving them to a single scoreboard to conserve
    space.
cpu/beta_cpu/free_list.hh:
    Mostly debugging statements.  Might be removed for performance in future.
cpu/beta_cpu/full_cpu.cc:
    Added in some debugging statements.  Updated BaseFullCPU to take
    a params object.
cpu/beta_cpu/full_cpu.hh:
    Added params class within BaseCPU that other param classes will be
    able to inherit from.  Updated typedefs to reflect change in location
    of time buffer structs and ref counted DynInst.
cpu/beta_cpu/iew.hh:
    Updated typedefs to reflect change in location of time buffer structs
    and use of ref counted DynInsts.
cpu/beta_cpu/iew_impl.hh:
    Added in load store queue, updated iew to be able to execute non-
    speculative instructions, instead of having them execute in commit.
cpu/beta_cpu/inst_queue.hh:
    Updated change to ref counted DynInsts.  Changed inst queue to hold
    non-speculative instructions as well, which are issued only when
    commit signals backwards that a nonspeculative instruction is at
    the head of the ROB.
cpu/beta_cpu/inst_queue_impl.hh:
    Updated to allow for non-speculative instructions to be in the inst
    queue.  Also added some debug functions.
cpu/beta_cpu/regfile.hh:
    Added debugging statements, changed formatting.
cpu/beta_cpu/rename.hh:
    Updated typedefs, added some functions to clean up code.
cpu/beta_cpu/rename_impl.hh:
    Moved some code into functions to make it easier to read.
cpu/beta_cpu/rename_map.cc:
    Changed int and float reg behavior to use a single flat namespace.  In
    the future, the rename maps can be combined to a single rename map to
    save space.
cpu/beta_cpu/rename_map.hh:
    Added destructor.
cpu/beta_cpu/rob.hh:
    Updated it with change from DynInst to ref counted DynInst.
cpu/beta_cpu/rob_impl.hh:
    Formatting, updated to use ref counted DynInst.
cpu/static_inst.hh:
    Updated forward declaration for AlphaDynInst now that it is templated.

--HG--
extra : convert_revision : 1045f240ee9b6a4bd368e1806aca029ebbdc6dd3

1 files changed, 36 insertions, 20 deletions

diff --git a/cpu/beta_cpu/full_cpu.hh b/cpu/beta_cpu/full_cpu.hh
index 00ff1f878..cf753ad67 100644
--- a/cpu/beta_cpu/full_cpu.hh
+++ b/cpu/beta_cpu/full_cpu.hh
@@ -16,6 +16,7 @@
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
 #include "cpu/base_cpu.hh"
+#include "cpu/exec_context.hh"
 #include "cpu/beta_cpu/cpu_policy.hh"
 #include "sim/process.hh"
 
@@ -28,17 +29,32 @@ class BaseFullCPU : public BaseCPU
 {
     //Stuff that's pretty ISA independent will go here.
   public:
+    class Params
+    {
+      public:
+#ifdef FULL_SYSTEM
+        std::string name;
+        int numberOfThreads;
+        Counter maxInstsAnyThread;
+        Counter maxInstsAllThreads;
+        Counter maxLoadsAnyThread;
+        Counter maxLoadsAllThreads;
+        System *_system;
+        Tick freq;
+#else
+        std::string name;
+        int numberOfThreads;
+        Counter maxInstsAnyThread;
+        Counter maxInstsAllThreads;
+        Counter maxLoadsAnyThread;
+        Counter maxLoadsAllThreads;
+#endif // FULL_SYSTEM
+    };
+
 #ifdef FULL_SYSTEM
-    BaseFullCPU(const std::string &_name, int _number_of_threads,
-                Counter max_insts_any_thread, Counter max_insts_all_threads,
-                Counter max_loads_any_thread, Counter max_loads_all_threads,
-                System *_system, Tick freq);
+    BaseFullCPU(Params &params);
 #else
-    BaseFullCPU(const std::string &_name, int _number_of_threads,
-                Counter max_insts_any_thread = 0,
-                Counter max_insts_all_threads = 0,
-                Counter max_loads_any_thread = 0,
-                Counter max_loads_all_threads = 0);
+    BaseFullCPU(Params &params);
 #endif // FULL_SYSTEM
 };
 
@@ -49,7 +65,7 @@ class FullBetaCPU : public BaseFullCPU
     //Put typedefs from the Impl here.
     typedef typename Impl::CPUPol CPUPolicy;
     typedef typename Impl::Params Params;
-    typedef typename Impl::DynInst DynInst;
+    typedef typename Impl::DynInstPtr DynInstPtr;
 
   public:
     enum Status {
@@ -162,7 +178,7 @@ class FullBetaCPU : public BaseFullCPU
     /** Function to add instruction onto the head of the list of the
      *  instructions.  Used when new instructions are fetched.
      */
-    void addInst(DynInst *inst);
+    void addInst(DynInstPtr &inst);
 
     /** Function to tell the CPU that an instruction has completed. */
     void instDone();
@@ -175,7 +191,7 @@ class FullBetaCPU : public BaseFullCPU
      *  @todo: Remove only up until that inst?  Squashed inst is most likely
      *  valid.
      */
-    void removeBackInst(DynInst *inst);
+    void removeBackInst(DynInstPtr &inst);
 
     /** Remove an instruction from the front of the list.  It is expected
      *  that there are no instructions in front of it (that is, none are older
@@ -184,7 +200,7 @@ class FullBetaCPU : public BaseFullCPU
      *  last instruction once it's verified that commit has the same ordering
      *  as the instruction list.
      */
-    void removeFrontInst(DynInst *inst);
+    void removeFrontInst(DynInstPtr &inst);
 
     /** Remove all instructions that are not currently in the ROB. */
     void removeInstsNotInROB();
@@ -198,11 +214,11 @@ class FullBetaCPU : public BaseFullCPU
      *  commit can tell the instruction queue that they have completed.
      *  Eventually this hack should be removed.
      */
-    void wakeDependents(DynInst *inst);
+    void wakeDependents(DynInstPtr &inst);
 
   public:
     /** List of all the instructions in flight. */
-    list<DynInst *> instList;
+    list<DynInstPtr> instList;
 
     //not sure these should be private.
   protected:
@@ -255,15 +271,15 @@ class FullBetaCPU : public BaseFullCPU
     /** Typedefs from the Impl to get the structs that each of the
      *  time buffers should use.
      */
-    typedef typename Impl::TimeStruct TimeStruct;
+    typedef typename CPUPolicy::TimeStruct TimeStruct;
 
-    typedef typename Impl::FetchStruct FetchStruct;
+    typedef typename CPUPolicy::FetchStruct FetchStruct;
 
-    typedef typename Impl::DecodeStruct DecodeStruct;
+    typedef typename CPUPolicy::DecodeStruct DecodeStruct;
 
-    typedef typename Impl::RenameStruct RenameStruct;
+    typedef typename CPUPolicy::RenameStruct RenameStruct;
 
-    typedef typename Impl::IEWStruct IEWStruct;
+    typedef typename CPUPolicy::IEWStruct IEWStruct;
 
     /** The main time buffer to do backwards communication. */
     TimeBuffer<TimeStruct> timeBuffer;