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authorKevin Lim <ktlim@umich.edu>2005-05-03 10:56:47 -0400
committerKevin Lim <ktlim@umich.edu>2005-05-03 10:56:47 -0400
commit61d95de4c886911fa0b7dc9d587ffe5b292b739e (patch)
treed70531683cfb9bdb7ab967a99fbb3d6e0c34814f /cpu/beta_cpu/full_cpu.hh
parent6191d3e4443b5337232a238a3a0dd5d11249e223 (diff)
downloadgem5-61d95de4c886911fa0b7dc9d587ffe5b292b739e.tar.xz
Large update of several parts of my code. The most notable change is the inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version.
SConscript: arch/isa_parser.py: cpu/base_dyn_inst.cc: Remove OOO CPU stuff. arch/alpha/faults.hh: Add fake memory fault. This will be removed eventually. arch/alpha/isa_desc: Change EA comp and Mem accessor to be const StaticInstPtrs. cpu/base_dyn_inst.hh: Update read/write calls to use load queue and store queue indices. cpu/beta_cpu/alpha_dyn_inst.hh: Change to const StaticInst in the register accessors. cpu/beta_cpu/alpha_dyn_inst_impl.hh: Update syscall code with thread numbers. cpu/beta_cpu/alpha_full_cpu.hh: Alter some of the full system code so it will compile without errors. cpu/beta_cpu/alpha_full_cpu_builder.cc: Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters. cpu/beta_cpu/alpha_full_cpu_impl.hh: Update some of the full system code so it compiles. cpu/beta_cpu/alpha_params.hh: cpu/beta_cpu/fetch_impl.hh: Remove asid. cpu/beta_cpu/comm.hh: Remove global history field. cpu/beta_cpu/commit.hh: Comment out rename map. cpu/beta_cpu/commit_impl.hh: Update some of the full system code so it compiles. Also change it so that it handles memory instructions properly. cpu/beta_cpu/cpu_policy.hh: Removed IQ from the IEW template parameter to make it more uniform. cpu/beta_cpu/decode.hh: Add debug function. cpu/beta_cpu/decode_impl.hh: Slight updates for decode in the case where it causes a squash. cpu/beta_cpu/fetch.hh: cpu/beta_cpu/rob.hh: Comment out unneccessary code. cpu/beta_cpu/full_cpu.cc: Changed some of the full system code so it compiles. Updated exec contexts and so forth to hopefully make multithreading easier. cpu/beta_cpu/full_cpu.hh: Updated some of the full system code to make it compile. cpu/beta_cpu/iew.cc: Removed IQ from template parameter to IEW. cpu/beta_cpu/iew.hh: Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue. cpu/beta_cpu/iew_impl.hh: New handling of memory instructions through the Load/Store queue. cpu/beta_cpu/inst_queue.hh: Updated comment. cpu/beta_cpu/inst_queue_impl.hh: Slightly different handling of memory instructions due to Load/Store queue. cpu/beta_cpu/regfile.hh: Updated full system code so it compiles. cpu/beta_cpu/rob_impl.hh: Moved some code around; no major functional changes. cpu/ooo_cpu/ooo_cpu.hh: Slight updates to OOO CPU; still does not work. cpu/static_inst.hh: Remove OOO CPU stuff. Change ea comp and mem acc to return const StaticInst. kern/kernel_stats.hh: Extra forward declares added due to compile error. --HG-- extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e
Diffstat (limited to 'cpu/beta_cpu/full_cpu.hh')
-rw-r--r--cpu/beta_cpu/full_cpu.hh44
1 files changed, 29 insertions, 15 deletions
diff --git a/cpu/beta_cpu/full_cpu.hh b/cpu/beta_cpu/full_cpu.hh
index 8ce32b7c7..85fc49371 100644
--- a/cpu/beta_cpu/full_cpu.hh
+++ b/cpu/beta_cpu/full_cpu.hh
@@ -5,11 +5,12 @@
//itself properly. Constructor. Derived alpha class. Threads!
// Avoid running stages and advancing queues if idle/stalled.
-#ifndef __SIMPLE_FULL_CPU_HH__
-#define __SIMPLE_FULL_CPU_HH__
+#ifndef __CPU_BETA_CPU_FULL_CPU_HH__
+#define __CPU_BETA_CPU_FULL_CPU_HH__
#include <iostream>
#include <list>
+#include <vector>
#include "cpu/beta_cpu/comm.hh"
@@ -20,6 +21,11 @@
#include "cpu/beta_cpu/cpu_policy.hh"
#include "sim/process.hh"
+#ifdef FULL_SYSTEM
+#include "arch/alpha/ev5.hh"
+using namespace EV5;
+#endif
+
class FunctionalMemory;
class Process;
@@ -34,6 +40,9 @@ class BaseFullCPU : public BaseCPU
#else
BaseFullCPU(Params &params);
#endif // FULL_SYSTEM
+
+ private:
+ int cpu_id;
};
template <class Impl>
@@ -41,6 +50,7 @@ class FullBetaCPU : public BaseFullCPU
{
public:
//Put typedefs from the Impl here.
+ typedef typename Impl::ISA ISA;
typedef typename Impl::CPUPol CPUPolicy;
typedef typename Impl::Params Params;
typedef typename Impl::DynInstPtr DynInstPtr;
@@ -114,19 +124,21 @@ class FullBetaCPU : public BaseFullCPU
bool validDataAddr(Addr addr) { return true; }
/** Get instruction asid. */
- int getInstAsid() { return ITB_ASN_ASN(regs.ipr[ISA::IPR_ITB_ASN]); }
+ int getInstAsid()
+ { return ITB_ASN_ASN(regFile.getIpr()[ISA::IPR_ITB_ASN]); }
/** Get data asid. */
- int getDataAsid() { return DTB_ASN_ASN(regs.ipr[ISA::IPR_DTB_ASN]); }
+ int getDataAsid()
+ { return DTB_ASN_ASN(regFile.getIpr()[ISA::IPR_DTB_ASN]); }
#else
bool validInstAddr(Addr addr)
- { return process->validInstAddr(addr); }
+ { return thread[0]->validInstAddr(addr); }
bool validDataAddr(Addr addr)
- { return process->validDataAddr(addr); }
+ { return thread[0]->validDataAddr(addr); }
- int getInstAsid() { return asid; }
- int getDataAsid() { return asid; }
+ int getInstAsid() { return thread[0]->asid; }
+ int getDataAsid() { return thread[0]->asid; }
#endif
@@ -284,7 +296,14 @@ class FullBetaCPU : public BaseFullCPU
ExecContext *xc;
/** Temporary function to get pointer to exec context. */
- ExecContext *xcBase() { return xc; }
+ ExecContext *xcBase()
+ {
+#ifdef FULL_SYSTEM
+ return system->execContexts[0];
+#else
+ return thread[0];
+#endif
+ }
InstSeqNum globalSeqNum;
@@ -299,12 +318,7 @@ class FullBetaCPU : public BaseFullCPU
// SWContext *swCtx;
#else
- Process *process;
-
- // Address space ID. Note that this is used for TIMING cache
- // simulation only; all functional memory accesses should use
- // one of the FunctionalMemory pointers above.
- short asid;
+ std::vector<ExecContext *> thread;
#endif
FunctionalMemory *mem;