Large update of several parts of my code. The most notable change is the inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version.

SConscript:
arch/isa_parser.py:
cpu/base_dyn_inst.cc:
    Remove OOO CPU stuff.
arch/alpha/faults.hh:
    Add fake memory fault.  This will be removed eventually.
arch/alpha/isa_desc:
    Change EA comp and Mem accessor to be const StaticInstPtrs.
cpu/base_dyn_inst.hh:
    Update read/write calls to use load queue and store queue indices.
cpu/beta_cpu/alpha_dyn_inst.hh:
    Change to const StaticInst in the register accessors.
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
    Update syscall code with thread numbers.
cpu/beta_cpu/alpha_full_cpu.hh:
    Alter some of the full system code so it will compile without errors.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
    Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
    Update some of the full system code so it compiles.
cpu/beta_cpu/alpha_params.hh:
cpu/beta_cpu/fetch_impl.hh:
    Remove asid.
cpu/beta_cpu/comm.hh:
    Remove global history field.
cpu/beta_cpu/commit.hh:
    Comment out rename map.
cpu/beta_cpu/commit_impl.hh:
    Update some of the full system code so it compiles.  Also change it so that it handles memory instructions properly.
cpu/beta_cpu/cpu_policy.hh:
    Removed IQ from the IEW template parameter to make it more uniform.
cpu/beta_cpu/decode.hh:
    Add debug function.
cpu/beta_cpu/decode_impl.hh:
    Slight updates for decode in the case where it causes a squash.
cpu/beta_cpu/fetch.hh:
cpu/beta_cpu/rob.hh:
    Comment out unneccessary code.
cpu/beta_cpu/full_cpu.cc:
    Changed some of the full system code so it compiles.  Updated exec contexts and so forth to hopefully make multithreading easier.
cpu/beta_cpu/full_cpu.hh:
    Updated some of the full system code to make it compile.
cpu/beta_cpu/iew.cc:
    Removed IQ from template parameter to IEW.
cpu/beta_cpu/iew.hh:
    Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue.
cpu/beta_cpu/iew_impl.hh:
    New handling of memory instructions through the Load/Store queue.
cpu/beta_cpu/inst_queue.hh:
    Updated comment.
cpu/beta_cpu/inst_queue_impl.hh:
    Slightly different handling of memory instructions due to Load/Store queue.
cpu/beta_cpu/regfile.hh:
    Updated full system code so it compiles.
cpu/beta_cpu/rob_impl.hh:
    Moved some code around; no major functional changes.
cpu/ooo_cpu/ooo_cpu.hh:
    Slight updates to OOO CPU; still does not work.
cpu/static_inst.hh:
    Remove OOO CPU stuff.  Change ea comp and mem acc to return const StaticInst.
kern/kernel_stats.hh:
    Extra forward declares added due to compile error.

--HG--
extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e

1 files changed, 35 insertions, 11 deletions

diff --git a/cpu/beta_cpu/iew.hh b/cpu/beta_cpu/iew.hh
index e3e7c6db5..1e5eb2244 100644
--- a/cpu/beta_cpu/iew.hh
+++ b/cpu/beta_cpu/iew.hh
@@ -14,7 +14,7 @@
 //Can IEW even stall?  Space should be available/allocated already...maybe
 //if there's not enough write ports on the ROB or waiting for CDB
 //arbitration.
-template<class Impl, class IQ>
+template<class Impl>
 class SimpleIEW
 {
   private:
@@ -25,6 +25,7 @@ class SimpleIEW
     typedef typename Impl::FullCPU FullCPU;
     typedef typename Impl::Params Params;
 
+    typedef typename CPUPol::IQ IQ;
     typedef typename CPUPol::RenameMap RenameMap;
     typedef typename CPUPol::LDSTQ LDSTQ;
 
@@ -33,6 +34,7 @@ class SimpleIEW
     typedef typename CPUPol::RenameStruct RenameStruct;
     typedef typename CPUPol::IssueStruct IssueStruct;
 
+    friend class Impl::FullCPU;
   public:
     enum Status {
         Running,
@@ -49,15 +51,17 @@ class SimpleIEW
     Status _wbStatus;
 
   public:
-    void squash();
-
-    void squashDueToBranch(DynInstPtr &inst);
-
-    void squashDueToMem(DynInstPtr &inst);
+    class WritebackEvent : public Event {
+      private:
+        DynInstPtr inst;
+        SimpleIEW<Impl> *iewStage;
 
-    void block();
+      public:
+        WritebackEvent(DynInstPtr &_inst, SimpleIEW<Impl> *_iew);
 
-    inline void unblock();
+        virtual void process();
+        virtual const char *description();
+    };
 
   public:
     SimpleIEW(Params &params);
@@ -74,17 +78,30 @@ class SimpleIEW
 
     void setRenameMap(RenameMap *rm_ptr);
 
-    void wakeDependents(DynInstPtr &inst);
+    void squash();
 
-    void tick();
+    void squashDueToBranch(DynInstPtr &inst);
 
-    void iew();
+    void squashDueToMem(DynInstPtr &inst);
+
+    void block();
+
+    inline void unblock();
+
+    void wakeDependents(DynInstPtr &inst);
+
+    void instToCommit(DynInstPtr &inst);
 
   private:
     void dispatchInsts();
 
     void executeInsts();
 
+  public:
+    void tick();
+
+    void iew();
+
     //Interfaces to objects inside and outside of IEW.
     /** Time buffer interface. */
     TimeBuffer<TimeStruct> *timeBuffer;
@@ -121,11 +138,18 @@ class SimpleIEW
     /** Skid buffer between rename and IEW. */
     std::queue<RenameStruct> skidBuffer;
 
+  protected:
     /** Instruction queue. */
     IQ instQueue;
 
     LDSTQ ldstQueue;
 
+#ifndef FULL_SYSTEM
+  public:
+    void lsqWriteback();
+#endif
+
+  private:
     /** Pointer to rename map.  Might not want this stage to directly
      *  access this though...
      */