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author | Kevin Lim <ktlim@umich.edu> | 2005-05-19 01:28:25 -0400 |
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committer | Kevin Lim <ktlim@umich.edu> | 2005-05-19 01:28:25 -0400 |
commit | c2fcac7c0dd8dff182cb262bdf35d5c67117aa42 (patch) | |
tree | fc8804bfbe1aa820c8afa446622b9ec8c658b75e /cpu/beta_cpu/iew_impl.hh | |
parent | e5721ce6777726fa54aee49be414233656bd98d1 (diff) | |
download | gem5-c2fcac7c0dd8dff182cb262bdf35d5c67117aa42.tar.xz |
Fix up code for initial release. The main bug that remains is properly forwarding data from stores to loads, specifically when they are of differing sizes.
cpu/base_dyn_inst.cc:
Remove unused commented out code.
cpu/base_dyn_inst.hh:
Fix up comments.
cpu/beta_cpu/2bit_local_pred.cc:
Reorder code to match header file.
cpu/beta_cpu/2bit_local_pred.hh:
Update comments.
cpu/beta_cpu/alpha_dyn_inst.hh:
Remove useless comments.
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
cpu/beta_cpu/alpha_full_cpu_impl.hh:
cpu/beta_cpu/comm.hh:
cpu/beta_cpu/iew_impl.hh:
Remove unused commented code.
cpu/beta_cpu/alpha_full_cpu.hh:
Remove obsolete comment.
cpu/beta_cpu/alpha_impl.hh:
cpu/beta_cpu/full_cpu.hh:
Alphabetize includes.
cpu/beta_cpu/bpred_unit.hh:
Remove unused global history code.
cpu/beta_cpu/btb.hh:
cpu/beta_cpu/free_list.hh:
Use full path in #defines.
cpu/beta_cpu/commit.hh:
cpu/beta_cpu/decode.hh:
Reorder functions.
cpu/beta_cpu/commit_impl.hh:
Remove obsolete commented code.
cpu/beta_cpu/fetch.hh:
Remove obsolete comments.
cpu/beta_cpu/fetch_impl.hh:
cpu/beta_cpu/rename_impl.hh:
Remove commented code.
cpu/beta_cpu/full_cpu.cc:
Remove useless defines.
cpu/beta_cpu/inst_queue.hh:
Use full path for #defines.
cpu/beta_cpu/inst_queue_impl.hh:
Reorder functions to match header file.
cpu/beta_cpu/mem_dep_unit.hh:
Use full path name for #defines.
cpu/beta_cpu/ras.hh:
Use full path names for #defines. Remove mod operation.
cpu/beta_cpu/regfile.hh:
Remove unused commented code, fix up current comments.
cpu/beta_cpu/tournament_pred.cc:
cpu/beta_cpu/tournament_pred.hh:
Update programming style.
--HG--
extra : convert_revision : fb9d18a853f58a1108ff827e3c123d5b52a0608a
Diffstat (limited to 'cpu/beta_cpu/iew_impl.hh')
-rw-r--r-- | cpu/beta_cpu/iew_impl.hh | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/cpu/beta_cpu/iew_impl.hh b/cpu/beta_cpu/iew_impl.hh index 086d39320..79dd809ad 100644 --- a/cpu/beta_cpu/iew_impl.hh +++ b/cpu/beta_cpu/iew_impl.hh @@ -361,20 +361,7 @@ SimpleIEW<Impl>::dispatchInsts() } else if (inst->isStore()) { ldstQueue.insertStore(inst); - // A bit of a hack. Set that it can commit so that - // the commit stage will try committing it, and then - // once commit realizes it's a store it will send back - // a signal to this stage to issue and execute that - // store. Change to be a bit that says the instruction - // has extra work to do at commit. -// inst->setCanCommit(); - -// instQueue.insertNonSpec(inst); - ++iewDispStoreInsts; -// ++iewDispNonSpecInsts; - -// continue; } else if (inst->isNonSpeculative()) { DPRINTF(IEW, "IEW: Issue: Nonspeculative instruction " "encountered, skipping.\n"); @@ -404,8 +391,6 @@ SimpleIEW<Impl>::dispatchInsts() DPRINTF(IEW, "IEW: Issue: Executed branch encountered, " "skipping.\n"); -// assert(inst->isDirectCtrl()); - inst->setIssued(); inst->setCanCommit(); @@ -614,10 +599,6 @@ SimpleIEW<Impl>::tick() } ++iewSquashCycles; - - // Also should advance its own time buffers if the stage ran. - // Not sure about this... -// issueToExecQueue.advance(); } else if (_status == Blocked) { // Continue to tell previous stage to stall. toRename->iewInfo.stall = true; @@ -654,14 +635,11 @@ SimpleIEW<Impl>::tick() // or store to commit. Also check if it's being told to execute a // nonspeculative instruction. // This is pretty inefficient... -// if (0/*fromCommit->commitInfo.commitIsStore*/) { if (!fromCommit->commitInfo.squash && !fromCommit->commitInfo.robSquashing) { ldstQueue.commitStores(fromCommit->commitInfo.doneSeqNum); -// } else if (fromCommit->commitInfo.commitIsLoad) { ldstQueue.commitLoads(fromCommit->commitInfo.doneSeqNum); } -// } if (fromCommit->commitInfo.nonSpecSeqNum != 0) { instQueue.scheduleNonSpec(fromCommit->commitInfo.nonSpecSeqNum); |