Initial light-weight OoO CPU checkin, along with gcc-3.4 fixes.

SConscript:
    Include new files.
arch/alpha/isa_desc:
    Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them.
arch/alpha/isa_traits.hh:
    Add enum for total number of data registers.
arch/isa_parser.py:
base/traceflags.py:
    Include new light-weight OoO CPU model.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
    Changes to abstract more away from the base dyn inst class.
cpu/beta_cpu/2bit_local_pred.cc:
cpu/beta_cpu/2bit_local_pred.hh:
cpu/beta_cpu/tournament_pred.cc:
cpu/beta_cpu/tournament_pred.hh:
    Remove redundant SatCounter class.
cpu/beta_cpu/alpha_dyn_inst.cc:
cpu/beta_cpu/alpha_full_cpu.cc:
cpu/beta_cpu/alpha_full_cpu.hh:
cpu/beta_cpu/bpred_unit.cc:
cpu/beta_cpu/inst_queue.cc:
cpu/beta_cpu/mem_dep_unit.cc:
cpu/beta_cpu/ras.cc:
cpu/beta_cpu/rename_map.cc:
cpu/beta_cpu/rename_map.hh:
cpu/beta_cpu/rob.cc:
    Fix for gcc-3.4
cpu/beta_cpu/alpha_dyn_inst.hh:
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
    Fixes for gcc-3.4.
    Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
    Make params match the current params inherited from BaseCPU.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
    Fixes for gcc-3.4
cpu/beta_cpu/full_cpu.cc:
    Use new params pointer in BaseCPU.
    Fix for gcc-3.4.
cpu/beta_cpu/full_cpu.hh:
    Use new params class from BaseCPU.
cpu/beta_cpu/iew_impl.hh:
    Remove unused function.
cpu/simple_cpu/simple_cpu.cc:
    Remove unused global variable.
cpu/static_inst.hh:
    Include OoODynInst for new lightweight OoO CPU

--HG--
extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa

1 files changed, 3 insertions, 3 deletions

diff --git a/cpu/beta_cpu/iew_impl.hh b/cpu/beta_cpu/iew_impl.hh
index b718e6aa0..1d072ab33 100644
--- a/cpu/beta_cpu/iew_impl.hh
+++ b/cpu/beta_cpu/iew_impl.hh
@@ -244,10 +244,10 @@ SimpleIEW<Impl, IQ>::squashDueToBranch(DynInstPtr &inst)
     // Also send PC update information back to prior stages.
     toCommit->squashedSeqNum = inst->seqNum;
     toCommit->mispredPC = inst->readPC();
-    toCommit->nextPC = inst->readCalcTarg();
+    toCommit->nextPC = inst->readNextPC();
     toCommit->branchMispredict = true;
     // Prediction was incorrect, so send back inverse.
-    toCommit->branchTaken = inst->readCalcTarg() !=
+    toCommit->branchTaken = inst->readNextPC() !=
         (inst->readPC() + sizeof(MachInst));
 }
 
@@ -265,7 +265,7 @@ SimpleIEW<Impl, IQ>::squashDueToMem(DynInstPtr &inst)
     toCommit->squash = true;
     // Also send PC update information back to prior stages.
     toCommit->squashedSeqNum = inst->seqNum;
-    toCommit->nextPC = inst->readCalcTarg();
+    toCommit->nextPC = inst->readNextPC();
 }
 
 template <class Impl, class IQ>