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| author | Kevin Lim <ktlim@umich.edu> | 2004-08-20 14:54:07 -0400 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2004-08-20 14:54:07 -0400 |
| commit | 04745696b6b523c5e90c335298099600d4a14a76 (patch) | |
| tree | 66b578f8c44355ccf8e970fe59b52554dde9d0ce /cpu/beta_cpu/inst_queue.cc | |
| parent | 8295a8050c1096dc560f4976724adada810e56e1 (diff) | |
| download | gem5-04745696b6b523c5e90c335298099600d4a14a76.tar.xz | |
Check in of new CPU. This checkin works under non-Fullsystem mode, with no caches.
SConscript:
Added new CPU files to build.
arch/alpha/isa_desc:
Changed rduniq and wruniq to be nonspeculative because the uniq register is not renamed.
arch/isa_parser.py:
Added new CPU exec method.
base/statistics.hh:
Minor change for namespace conflict. Probably can change back one the new CPU files are cleaned up.
base/traceflags.py:
Added new CPU trace flags.
cpu/static_inst.hh:
Changed static inst to use a file that defines the execute functions.
--HG--
extra : convert_revision : bd4ce34361308280168324817fc1258dd253e519
Diffstat (limited to 'cpu/beta_cpu/inst_queue.cc')
| -rw-r--r-- | cpu/beta_cpu/inst_queue.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/cpu/beta_cpu/inst_queue.cc b/cpu/beta_cpu/inst_queue.cc new file mode 100644 index 000000000..43b0a4572 --- /dev/null +++ b/cpu/beta_cpu/inst_queue.cc @@ -0,0 +1,7 @@ + +#include "cpu/beta_cpu/alpha_dyn_inst.hh" +#include "cpu/beta_cpu/alpha_impl.hh" +#include "cpu/beta_cpu/inst_queue_impl.hh" + +// Force instantiation of InstructionQueue. +template InstructionQueue<AlphaSimpleImpl>; |