shuffle files around for new directory structure

--HG--
rename : cpu/base_cpu.cc => cpu/base.cc
rename : cpu/base_cpu.hh => cpu/base.hh
rename : cpu/beta_cpu/2bit_local_pred.cc => cpu/o3/2bit_local_pred.cc
rename : cpu/beta_cpu/2bit_local_pred.hh => cpu/o3/2bit_local_pred.hh
rename : cpu/beta_cpu/alpha_full_cpu.cc => cpu/o3/alpha_cpu.cc
rename : cpu/beta_cpu/alpha_full_cpu.hh => cpu/o3/alpha_cpu.hh
rename : cpu/beta_cpu/alpha_full_cpu_builder.cc => cpu/o3/alpha_cpu_builder.cc
rename : cpu/beta_cpu/alpha_full_cpu_impl.hh => cpu/o3/alpha_cpu_impl.hh
rename : cpu/beta_cpu/alpha_dyn_inst.cc => cpu/o3/alpha_dyn_inst.cc
rename : cpu/beta_cpu/alpha_dyn_inst.hh => cpu/o3/alpha_dyn_inst.hh
rename : cpu/beta_cpu/alpha_dyn_inst_impl.hh => cpu/o3/alpha_dyn_inst_impl.hh
rename : cpu/beta_cpu/alpha_impl.hh => cpu/o3/alpha_impl.hh
rename : cpu/beta_cpu/alpha_params.hh => cpu/o3/alpha_params.hh
rename : cpu/beta_cpu/bpred_unit.cc => cpu/o3/bpred_unit.cc
rename : cpu/beta_cpu/bpred_unit.hh => cpu/o3/bpred_unit.hh
rename : cpu/beta_cpu/bpred_unit_impl.hh => cpu/o3/bpred_unit_impl.hh
rename : cpu/beta_cpu/btb.cc => cpu/o3/btb.cc
rename : cpu/beta_cpu/btb.hh => cpu/o3/btb.hh
rename : cpu/beta_cpu/comm.hh => cpu/o3/comm.hh
rename : cpu/beta_cpu/commit.cc => cpu/o3/commit.cc
rename : cpu/beta_cpu/commit.hh => cpu/o3/commit.hh
rename : cpu/beta_cpu/commit_impl.hh => cpu/o3/commit_impl.hh
rename : cpu/beta_cpu/full_cpu.cc => cpu/o3/cpu.cc
rename : cpu/beta_cpu/full_cpu.hh => cpu/o3/cpu.hh
rename : cpu/beta_cpu/cpu_policy.hh => cpu/o3/cpu_policy.hh
rename : cpu/beta_cpu/decode.cc => cpu/o3/decode.cc
rename : cpu/beta_cpu/decode.hh => cpu/o3/decode.hh
rename : cpu/beta_cpu/decode_impl.hh => cpu/o3/decode_impl.hh
rename : cpu/beta_cpu/fetch.cc => cpu/o3/fetch.cc
rename : cpu/beta_cpu/fetch.hh => cpu/o3/fetch.hh
rename : cpu/beta_cpu/fetch_impl.hh => cpu/o3/fetch_impl.hh
rename : cpu/beta_cpu/free_list.cc => cpu/o3/free_list.cc
rename : cpu/beta_cpu/free_list.hh => cpu/o3/free_list.hh
rename : cpu/beta_cpu/iew.cc => cpu/o3/iew.cc
rename : cpu/beta_cpu/iew.hh => cpu/o3/iew.hh
rename : cpu/beta_cpu/iew_impl.hh => cpu/o3/iew_impl.hh
rename : cpu/beta_cpu/inst_queue.cc => cpu/o3/inst_queue.cc
rename : cpu/beta_cpu/inst_queue.hh => cpu/o3/inst_queue.hh
rename : cpu/beta_cpu/inst_queue_impl.hh => cpu/o3/inst_queue_impl.hh
rename : cpu/beta_cpu/mem_dep_unit.cc => cpu/o3/mem_dep_unit.cc
rename : cpu/beta_cpu/mem_dep_unit.hh => cpu/o3/mem_dep_unit.hh
rename : cpu/beta_cpu/mem_dep_unit_impl.hh => cpu/o3/mem_dep_unit_impl.hh
rename : cpu/beta_cpu/ras.cc => cpu/o3/ras.cc
rename : cpu/beta_cpu/ras.hh => cpu/o3/ras.hh
rename : cpu/beta_cpu/regfile.hh => cpu/o3/regfile.hh
rename : cpu/beta_cpu/rename.cc => cpu/o3/rename.cc
rename : cpu/beta_cpu/rename.hh => cpu/o3/rename.hh
rename : cpu/beta_cpu/rename_impl.hh => cpu/o3/rename_impl.hh
rename : cpu/beta_cpu/rename_map.cc => cpu/o3/rename_map.cc
rename : cpu/beta_cpu/rename_map.hh => cpu/o3/rename_map.hh
rename : cpu/beta_cpu/rob.cc => cpu/o3/rob.cc
rename : cpu/beta_cpu/rob.hh => cpu/o3/rob.hh
rename : cpu/beta_cpu/rob_impl.hh => cpu/o3/rob_impl.hh
rename : cpu/beta_cpu/sat_counter.cc => cpu/o3/sat_counter.cc
rename : cpu/beta_cpu/sat_counter.hh => cpu/o3/sat_counter.hh
rename : cpu/beta_cpu/store_set.cc => cpu/o3/store_set.cc
rename : cpu/beta_cpu/store_set.hh => cpu/o3/store_set.hh
rename : cpu/beta_cpu/tournament_pred.cc => cpu/o3/tournament_pred.cc
rename : cpu/beta_cpu/tournament_pred.hh => cpu/o3/tournament_pred.hh
rename : cpu/ooo_cpu/ooo_cpu.cc => cpu/ozone/cpu.cc
rename : cpu/ooo_cpu/ooo_cpu.hh => cpu/ozone/cpu.hh
rename : cpu/ooo_cpu/ooo_impl.hh => cpu/ozone/cpu_impl.hh
rename : cpu/ooo_cpu/ea_list.cc => cpu/ozone/ea_list.cc
rename : cpu/ooo_cpu/ea_list.hh => cpu/ozone/ea_list.hh
rename : cpu/simple_cpu/simple_cpu.cc => cpu/simple/cpu.cc
rename : cpu/simple_cpu/simple_cpu.hh => cpu/simple/cpu.hh
rename : cpu/full_cpu/smt.hh => cpu/smt.hh
rename : cpu/full_cpu/op_class.hh => encumbered/cpu/full/op_class.hh
extra : convert_revision : c4a891d8d6d3e0e9e5ea56be47d851da44d8c032

1 files changed, 0 insertions, 419 deletions

diff --git a/cpu/beta_cpu/mem_dep_unit_impl.hh b/cpu/beta_cpu/mem_dep_unit_impl.hh
deleted file mode 100644
index e8cd88ba7..000000000
--- a/cpu/beta_cpu/mem_dep_unit_impl.hh
+++ /dev/null
@@ -1,419 +0,0 @@
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <map>
-
-#include "cpu/beta_cpu/mem_dep_unit.hh"
-
-template <class MemDepPred, class Impl>
-MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params &params)
-    : depPred(params.SSITSize, params.LFSTSize)
-{
-    DPRINTF(MemDepUnit, "MemDepUnit: Creating MemDepUnit object.\n");
-}
-
-template <class MemDepPred, class Impl>
-void
-MemDepUnit<MemDepPred, Impl>::regStats()
-{
-    insertedLoads
-        .name(name() + ".memDep.insertedLoads")
-        .desc("Number of loads inserted to the mem dependence unit.");
-
-    insertedStores
-        .name(name() + ".memDep.insertedStores")
-        .desc("Number of stores inserted to the mem dependence unit.");
-
-    conflictingLoads
-        .name(name() + ".memDep.conflictingLoads")
-        .desc("Number of conflicting loads.");
-
-    conflictingStores
-        .name(name() + ".memDep.conflictingStores")
-        .desc("Number of conflicting stores.");
-}
-
-template <class MemDepPred, class Impl>
-void
-MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
-{
-    InstSeqNum inst_seq_num = inst->seqNum;
-
-    Dependency unresolved_dependencies(inst_seq_num);
-
-    InstSeqNum producing_store = depPred.checkInst(inst->readPC());
-
-    if (producing_store == 0 ||
-        storeDependents.find(producing_store) == storeDependents.end()) {
-
-        DPRINTF(MemDepUnit, "MemDepUnit: No dependency for inst PC "
-                "%#x.\n", inst->readPC());
-
-        unresolved_dependencies.storeDep = storeDependents.end();
-
-        if (inst->readyToIssue()) {
-            readyInsts.insert(inst_seq_num);
-        } else {
-            unresolved_dependencies.memDepReady = true;
-
-            waitingInsts.insert(unresolved_dependencies);
-        }
-    } else {
-        DPRINTF(MemDepUnit, "MemDepUnit: Adding to dependency list; "
-                "inst PC %#x is dependent on seq num %i.\n",
-                inst->readPC(), producing_store);
-
-        if (inst->readyToIssue()) {
-            unresolved_dependencies.regsReady = true;
-        }
-
-        // Find the store that this instruction is dependent on.
-        sd_it_t store_loc = storeDependents.find(producing_store);
-
-        assert(store_loc != storeDependents.end());
-
-        // Record the location of the store that this instruction is
-        // dependent on.
-        unresolved_dependencies.storeDep = store_loc;
-
-        // If it's not already ready, then add it to the renamed
-        // list and the dependencies.
-        dep_it_t inst_loc =
-            (waitingInsts.insert(unresolved_dependencies)).first;
-
-        // Add this instruction to the list of dependents.
-        (*store_loc).second.push_back(inst_loc);
-
-        assert(!(*store_loc).second.empty());
-
-        if (inst->isLoad()) {
-            ++conflictingLoads;
-        } else {
-            ++conflictingStores;
-        }
-    }
-
-    if (inst->isStore()) {
-        DPRINTF(MemDepUnit, "MemDepUnit: Inserting store PC %#x.\n",
-                inst->readPC());
-
-        depPred.insertStore(inst->readPC(), inst_seq_num);
-
-        // Make sure this store isn't already in this list.
-        assert(storeDependents.find(inst_seq_num) == storeDependents.end());
-
-        // Put a dependency entry in at the store's sequence number.
-        // Uh, not sure how this works...I want to create an entry but
-        // I don't have anything to put into the value yet.
-        storeDependents[inst_seq_num];
-
-        assert(storeDependents.size() != 0);
-
-        ++insertedStores;
-
-    } else if (inst->isLoad()) {
-        ++insertedLoads;
-    } else {
-        panic("MemDepUnit: Unknown type! (most likely a barrier).");
-    }
-
-    memInsts[inst_seq_num] = inst;
-}
-
-template <class MemDepPred, class Impl>
-void
-MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
-{
-    InstSeqNum inst_seq_num = inst->seqNum;
-
-    Dependency non_spec_inst(inst_seq_num);
-
-    non_spec_inst.storeDep = storeDependents.end();
-
-    waitingInsts.insert(non_spec_inst);
-
-    // Might want to turn this part into an inline function or something.
-    // It's shared between both insert functions.
-    if (inst->isStore()) {
-        DPRINTF(MemDepUnit, "MemDepUnit: Inserting store PC %#x.\n",
-                inst->readPC());
-
-        depPred.insertStore(inst->readPC(), inst_seq_num);
-
-        // Make sure this store isn't already in this list.
-        assert(storeDependents.find(inst_seq_num) == storeDependents.end());
-
-        // Put a dependency entry in at the store's sequence number.
-        // Uh, not sure how this works...I want to create an entry but
-        // I don't have anything to put into the value yet.
-        storeDependents[inst_seq_num];
-
-        assert(storeDependents.size() != 0);
-
-        ++insertedStores;
-
-    } else if (inst->isLoad()) {
-        ++insertedLoads;
-    } else {
-        panic("MemDepUnit: Unknown type! (most likely a barrier).");
-    }
-
-    memInsts[inst_seq_num] = inst;
-}
-
-template <class MemDepPred, class Impl>
-typename Impl::DynInstPtr &
-MemDepUnit<MemDepPred, Impl>::top()
-{
-    topInst = memInsts.find( (*readyInsts.begin()) );
-
-    DPRINTF(MemDepUnit, "MemDepUnit: Top instruction is PC %#x.\n",
-            (*topInst).second->readPC());
-
-    return (*topInst).second;
-}
-
-template <class MemDepPred, class Impl>
-void
-MemDepUnit<MemDepPred, Impl>::pop()
-{
-    DPRINTF(MemDepUnit, "MemDepUnit: Removing instruction PC %#x.\n",
-            (*topInst).second->readPC());
-
-    wakeDependents((*topInst).second);
-
-    issue((*topInst).second);
-
-    memInsts.erase(topInst);
-
-    topInst = memInsts.end();
-}
-
-template <class MemDepPred, class Impl>
-void
-MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
-{
-    DPRINTF(MemDepUnit, "MemDepUnit: Marking registers as ready for "
-            "instruction PC %#x.\n",
-            inst->readPC());
-
-    InstSeqNum inst_seq_num = inst->seqNum;
-
-    Dependency inst_to_find(inst_seq_num);
-
-    dep_it_t waiting_inst = waitingInsts.find(inst_to_find);
-
-    assert(waiting_inst != waitingInsts.end());
-
-    if ((*waiting_inst).memDepReady) {
-        DPRINTF(MemDepUnit, "MemDepUnit: Instruction has its memory "
-                "dependencies resolved, adding it to the ready list.\n");
-
-        moveToReady(waiting_inst);
-    } else {
-        DPRINTF(MemDepUnit, "MemDepUnit: Instruction still waiting on "
-                "memory dependency.\n");
-
-        (*waiting_inst).regsReady = true;
-    }
-}
-
-template <class MemDepPred, class Impl>
-void
-MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
-{
-    DPRINTF(MemDepUnit, "MemDepUnit: Marking non speculative "
-            "instruction PC %#x as ready.\n",
-            inst->readPC());
-
-    InstSeqNum inst_seq_num = inst->seqNum;
-
-    Dependency inst_to_find(inst_seq_num);
-
-    dep_it_t waiting_inst = waitingInsts.find(inst_to_find);
-
-    assert(waiting_inst != waitingInsts.end());
-
-    moveToReady(waiting_inst);
-}
-
-template <class MemDepPred, class Impl>
-void
-MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
-{
-    assert(readyInsts.find(inst->seqNum) != readyInsts.end());
-
-    DPRINTF(MemDepUnit, "MemDepUnit: Issuing instruction PC %#x.\n",
-            inst->readPC());
-
-    // Remove the instruction from the ready list.
-    readyInsts.erase(inst->seqNum);
-
-    depPred.issued(inst->readPC(), inst->seqNum, inst->isStore());
-}
-
-template <class MemDepPred, class Impl>
-void
-MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
-{
-    // Only stores have dependents.
-    if (!inst->isStore()) {
-        return;
-    }
-
-    // Wake any dependencies.
-    sd_it_t sd_it = storeDependents.find(inst->seqNum);
-
-    // If there's no entry, then return.  Really there should only be
-    // no entry if the instruction is a load.
-    if (sd_it == storeDependents.end()) {
-        DPRINTF(MemDepUnit, "MemDepUnit: Instruction PC %#x, sequence "
-                "number %i has no dependents.\n",
-                inst->readPC(), inst->seqNum);
-
-        return;
-    }
-
-    for (int i = 0; i < (*sd_it).second.size(); ++i ) {
-        dep_it_t woken_inst = (*sd_it).second[i];
-
-        DPRINTF(MemDepUnit, "MemDepUnit: Waking up a dependent inst, "
-                "sequence number %i.\n",
-                (*woken_inst).seqNum);
-#if 0
-        // Should we have reached instructions that are actually squashed,
-        // there will be no more useful instructions in this dependency
-        // list.  Break out early.
-        if (waitingInsts.find(woken_inst) == waitingInsts.end()) {
-            DPRINTF(MemDepUnit, "MemDepUnit: Dependents on inst PC %#x "
-                    "are squashed, starting at SN %i.  Breaking early.\n",
-                    inst->readPC(), woken_inst);
-            break;
-        }
-#endif
-
-        if ((*woken_inst).regsReady) {
-            moveToReady(woken_inst);
-        } else {
-            (*woken_inst).memDepReady = true;
-        }
-    }
-
-    storeDependents.erase(sd_it);
-}
-
-template <class MemDepPred, class Impl>
-void
-MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num)
-{
-
-    if (!waitingInsts.empty()) {
-        dep_it_t waiting_it = waitingInsts.end();
-
-        --waiting_it;
-
-        // Remove entries from the renamed list as long as we haven't reached
-        // the end and the entries continue to be younger than the squashed.
-        while (!waitingInsts.empty() &&
-               (*waiting_it).seqNum > squashed_num)
-        {
-            if (!(*waiting_it).memDepReady &&
-                (*waiting_it).storeDep != storeDependents.end()) {
-                sd_it_t sd_it = (*waiting_it).storeDep;
-
-                // Make sure the iterator that the store has pointing
-                // back is actually to this instruction.
-                assert((*sd_it).second.back() == waiting_it);
-
-                // Now remove this from the store's list of dependent
-                // instructions.
-                (*sd_it).second.pop_back();
-            }
-
-            waitingInsts.erase(waiting_it--);
-        }
-    }
-
-    if (!readyInsts.empty()) {
-        sn_it_t ready_it = readyInsts.end();
-
-        --ready_it;
-
-        // Same for the ready list.
-        while (!readyInsts.empty() &&
-               (*ready_it) > squashed_num)
-        {
-            readyInsts.erase(ready_it--);
-        }
-    }
-
-    if (!storeDependents.empty()) {
-        sd_it_t dep_it = storeDependents.end();
-
-        --dep_it;
-
-        // Same for the dependencies list.
-        while (!storeDependents.empty() &&
-               (*dep_it).first > squashed_num)
-        {
-            // This store's list of dependent instructions should be empty.
-            assert((*dep_it).second.empty());
-
-            storeDependents.erase(dep_it--);
-        }
-    }
-
-    // Tell the dependency predictor to squash as well.
-    depPred.squash(squashed_num);
-}
-
-template <class MemDepPred, class Impl>
-void
-MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
-                                        DynInstPtr &violating_load)
-{
-    DPRINTF(MemDepUnit, "MemDepUnit: Passing violating PCs to store sets,"
-            " load: %#x, store: %#x\n", violating_load->readPC(),
-            store_inst->readPC());
-    // Tell the memory dependence unit of the violation.
-    depPred.violation(violating_load->readPC(), store_inst->readPC());
-}
-
-template <class MemDepPred, class Impl>
-inline void
-MemDepUnit<MemDepPred, Impl>::moveToReady(dep_it_t &woken_inst)
-{
-    DPRINTF(MemDepUnit, "MemDepUnit: Adding instruction sequence number %i "
-            "to the ready list.\n", (*woken_inst).seqNum);
-
-    // Add it to the ready list.
-    readyInsts.insert((*woken_inst).seqNum);
-
-    // Remove it from the waiting instructions.
-    waitingInsts.erase(woken_inst);
-}