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author | Kevin Lim <ktlim@umich.edu> | 2004-09-23 14:06:03 -0400 |
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committer | Kevin Lim <ktlim@umich.edu> | 2004-09-23 14:06:03 -0400 |
commit | e3fb9afa79e37cb8c60a48b9ff3976665c2c7675 (patch) | |
tree | a2f252590b6e68659c4b97c6478463eb8d8591ab /cpu/beta_cpu/mem_dep_unit_impl.hh | |
parent | 04745696b6b523c5e90c335298099600d4a14a76 (diff) | |
download | gem5-e3fb9afa79e37cb8c60a48b9ff3976665c2c7675.tar.xz |
Update to make multiple instruction issue and different latencies work.
Also change to ref counted DynInst.
SConscript:
Add branch predictor, BTB, load store queue, and storesets.
arch/isa_parser.py:
Specify the template parameter for AlphaDynInst
base/traceflags.py:
Add load store queue, store set, and mem dependence unit to the
list of trace flags.
cpu/base_dyn_inst.cc:
Change formating, add in debug statement.
cpu/base_dyn_inst.hh:
Change DynInst to be RefCounted, add flag to clear whether or not this
instruction can commit. This is likely to be removed in the future.
cpu/beta_cpu/alpha_dyn_inst.cc:
AlphaDynInst has been changed to be templated, so now this CC file
is just used to force instantiations of AlphaDynInst.
cpu/beta_cpu/alpha_dyn_inst.hh:
Changed AlphaDynInst to be templated on Impl. Removed some unnecessary
functions.
cpu/beta_cpu/alpha_full_cpu.cc:
AlphaFullCPU has been changed to be templated, so this CC file is now
just used to force instantation of AlphaFullCPU.
cpu/beta_cpu/alpha_full_cpu.hh:
Change AlphaFullCPU to be templated on Impl.
cpu/beta_cpu/alpha_impl.hh:
Update it to reflect AlphaDynInst and AlphaFullCPU being templated
on Impl. Also removed time buffers from here, as they are really
a part of the CPU and are thus in the CPU policy now.
cpu/beta_cpu/alpha_params.hh:
Make AlphaSimpleParams inherit from the BaseFullCPU so that it doesn't
need to specifically declare any parameters that are already in the
BaseFullCPU.
cpu/beta_cpu/comm.hh:
Changed the structure of the time buffer communication structs. Now
they include the size of the packet of instructions it is sending.
Added some parameters to the backwards communication struct, mainly
for squashing.
cpu/beta_cpu/commit.hh:
Update typenames to reflect change in location of time buffer structs.
Update DynInst to DynInstPtr (it is refcounted now).
cpu/beta_cpu/commit_impl.hh:
Formatting changes mainly. Also sends back proper information
on branch mispredicts so that the bpred unit can update itself.
Updated behavior for non-speculative instructions (stores, any
other non-spec instructions): once they reach the head of the ROB,
the ROB signals back to the IQ that it can go ahead and issue the
non-speculative instruction. The instruction itself is updated so that
commit won't try to commit it again until it is done executing.
cpu/beta_cpu/cpu_policy.hh:
Added branch prediction unit, mem dependence prediction unit, load
store queue. Moved time buffer structs from AlphaSimpleImpl to here.
cpu/beta_cpu/decode.hh:
Changed typedefs to reflect change in location of time buffer structs
and also the change from DynInst to ref counted DynInstPtr.
cpu/beta_cpu/decode_impl.hh:
Continues to buffer instructions even while unblocking now. Changed
how it loops through groups of instructions so it can properly block
during the middle of a group of instructions.
cpu/beta_cpu/fetch.hh:
Changed typedefs to reflect change in location of time buffer structs
and the change to ref counted DynInsts. Also added in branch
brediction unit.
cpu/beta_cpu/fetch_impl.hh:
Add in branch prediction. Changed how fetch checks inputs and its
current state to make for easier logic.
cpu/beta_cpu/free_list.cc:
Changed int regs and float regs to logically use one flat namespace.
Future change will be moving them to a single scoreboard to conserve
space.
cpu/beta_cpu/free_list.hh:
Mostly debugging statements. Might be removed for performance in future.
cpu/beta_cpu/full_cpu.cc:
Added in some debugging statements. Updated BaseFullCPU to take
a params object.
cpu/beta_cpu/full_cpu.hh:
Added params class within BaseCPU that other param classes will be
able to inherit from. Updated typedefs to reflect change in location
of time buffer structs and ref counted DynInst.
cpu/beta_cpu/iew.hh:
Updated typedefs to reflect change in location of time buffer structs
and use of ref counted DynInsts.
cpu/beta_cpu/iew_impl.hh:
Added in load store queue, updated iew to be able to execute non-
speculative instructions, instead of having them execute in commit.
cpu/beta_cpu/inst_queue.hh:
Updated change to ref counted DynInsts. Changed inst queue to hold
non-speculative instructions as well, which are issued only when
commit signals backwards that a nonspeculative instruction is at
the head of the ROB.
cpu/beta_cpu/inst_queue_impl.hh:
Updated to allow for non-speculative instructions to be in the inst
queue. Also added some debug functions.
cpu/beta_cpu/regfile.hh:
Added debugging statements, changed formatting.
cpu/beta_cpu/rename.hh:
Updated typedefs, added some functions to clean up code.
cpu/beta_cpu/rename_impl.hh:
Moved some code into functions to make it easier to read.
cpu/beta_cpu/rename_map.cc:
Changed int and float reg behavior to use a single flat namespace. In
the future, the rename maps can be combined to a single rename map to
save space.
cpu/beta_cpu/rename_map.hh:
Added destructor.
cpu/beta_cpu/rob.hh:
Updated it with change from DynInst to ref counted DynInst.
cpu/beta_cpu/rob_impl.hh:
Formatting, updated to use ref counted DynInst.
cpu/static_inst.hh:
Updated forward declaration for AlphaDynInst now that it is templated.
--HG--
extra : convert_revision : 1045f240ee9b6a4bd368e1806aca029ebbdc6dd3
Diffstat (limited to 'cpu/beta_cpu/mem_dep_unit_impl.hh')
-rw-r--r-- | cpu/beta_cpu/mem_dep_unit_impl.hh | 166 |
1 files changed, 166 insertions, 0 deletions
diff --git a/cpu/beta_cpu/mem_dep_unit_impl.hh b/cpu/beta_cpu/mem_dep_unit_impl.hh new file mode 100644 index 000000000..4299acb7a --- /dev/null +++ b/cpu/beta_cpu/mem_dep_unit_impl.hh @@ -0,0 +1,166 @@ + +#include <map> + +#include "cpu/beta_cpu/mem_dep_unit.hh" + +// Hack: dependence predictor sizes are hardcoded. +template <class MemDepPred, class Impl> +MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params ¶ms) + : depPred(4028, 128) +{ + DPRINTF(MemDepUnit, "MemDepUnit: Creating MemDepUnit object.\n"); +} + +template <class MemDepPred, class Impl> +void +MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst) +{ + InstSeqNum inst_seq_num = inst->seqNum; + + + InstSeqNum producing_store = depPred.checkInst(inst->readPC()); + + if (producing_store == 0 || + dependencies.find(producing_store) == dependencies.end()) { + readyInsts.insert(inst_seq_num); + } else { + // If it's not already ready, then add it to the renamed + // list and the dependencies. + renamedInsts.insert(inst_seq_num); + + dependencies[producing_store].push_back(inst_seq_num); + } + + if (inst->isStore()) { + depPred.insertStore(inst->readPC(), inst_seq_num); + + // Make sure this store isn't already in this list. + assert(dependencies.find(inst_seq_num) == dependencies.end()); + + // Put a dependency entry in at the store's sequence number. + // Uh, not sure how this works...I want to create an entry but + // I don't have anything to put into the value yet. + dependencies[inst_seq_num]; + } else if (!inst->isLoad()) { + panic("MemDepUnit: Unknown type! (most likely a barrier)."); + } +} + +template <class MemDepPred, class Impl> +bool +MemDepUnit<MemDepPred, Impl>::readyToIssue(DynInstPtr &inst) +{ + InstSeqNum inst_seq_num = inst->seqNum; + + if (readyInsts.find(inst_seq_num) == readyInsts.end()) { + return false; + } else { + return true; + } +} + +template <class MemDepPred, class Impl> +void +MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst) +{ + assert(readyInsts.find(inst->seqNum) != readyInsts.end()); + + // Remove the instruction from the ready list. + readyInsts.erase(inst->seqNum); +} + +template <class MemDepPred, class Impl> +void +MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst) +{ + // Wake any dependencies. + dep_it_t dep_it = dependencies.find(inst); + + // If there's no entry, then return. Really there should only be + // no entry if the instruction is a load. + if (dep_it == dependencies.end()) { + return; + } + + assert(inst->isStore()); + + for(int i = 0; i < (*dep_it).second.size(); ++i ) { + InstSeqNum woken_inst = (*dep_it).second[i]; + + // Should we have reached instructions that are actually squashed, + // there will be no more useful instructions in this dependency + // list. Break out early. + if (renamedInsts.find(woken_inst) == renamedInsts.end()) { + DPRINTF(MemDepUnit, "MemDepUnit: Dependents on inst PC %#x " + "are squashed, starting at SN %i. Breaking early.\n", + inst->readPC(), woken_inst); + break; + } + + // Remove it from the renamed instructions. + renamedInsts.erase(woken_inst); + + // Add it to the ready list. + readyInsts.insert(woken_inst); + } + + dependencies.erase(dep_it); +} + +template <class MemDepPred, class Impl> +void +MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num) +{ + + if (!renamedInsts.empty()) { + sn_it_t renamed_it = renamedInsts.end(); + + --renamed_it; + + // Remove entries from the renamed list as long as we haven't reached + // the end and the entries continue to be younger than the squashed. + while (!renamedInsts.empty() && + (*renamed_it) > squashed_num) + { + renamedInsts.erase(renamed_it--); + } + } + + if (!readyInsts.empty()) { + sn_it_t ready_it = readyInsts.end(); + + --ready_it; + + // Same for the ready list. + while (!readyInsts.empty() && + (*ready_it) > squashed_num) + { + readyInsts.erase(ready_it--); + } + } + + if (!dependencies.empty()) { + dep_it_t dep_it = dependencies.end(); + + --dep_it; + + // Same for the dependencies list. + while (!dependencies.empty() && + (*dep_it).first > squashed_num) + { + dependencies.erase(dep_it--); + } + } + + // Tell the dependency predictor to squash as well. + depPred.squash(squashed_num); +} + +template <class MemDepPred, class Impl> +void +MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst, + DynInstPtr &violating_load) +{ + // Tell the memory dependence unit of the violation. + depPred.violation(violating_load->readPC(), store_inst->readPC()); +} |