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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2005-05-20 17:13:37 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2005-05-20 17:13:37 -0400 |
| commit | 9725c13a0b0e444c996f27b55aa0d5e6570fab97 (patch) | |
| tree | 0b56479563a922b851a4cfad64eb81d6862549d6 /cpu/beta_cpu/regfile.hh | |
| parent | c2fcac7c0dd8dff182cb262bdf35d5c67117aa42 (diff) | |
| download | gem5-9725c13a0b0e444c996f27b55aa0d5e6570fab97.tar.xz | |
Minor changes to get new cpu to compile with FULL_SYSTEM.
cpu/beta_cpu/full_cpu.hh:
Make cpu_id protected rather than private so derived
classes can access it.
cpu/beta_cpu/regfile.hh:
Get rid of troublesome debugging statement.
--HG--
extra : convert_revision : ae1f841697ea8d736579b8278eaf8fc6bdf3b6c5
Diffstat (limited to 'cpu/beta_cpu/regfile.hh')
| -rw-r--r-- | cpu/beta_cpu/regfile.hh | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/cpu/beta_cpu/regfile.hh b/cpu/beta_cpu/regfile.hh index d7664707d..b88a33bfb 100644 --- a/cpu/beta_cpu/regfile.hh +++ b/cpu/beta_cpu/regfile.hh @@ -428,11 +428,6 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val) break; case ISA::IPR_IPLR: -#ifdef DEBUG - if (break_ipl != -1 && break_ipl == (val & 0x1f)) - debug_break(); -#endif - // only write least significant five bits - interrupt level ipr[idx] = val & 0x1f; break; |