Update to make multiple instruction issue and different latencies work.

Also change to ref counted DynInst.

SConscript:
    Add branch predictor, BTB, load store queue, and storesets.
arch/isa_parser.py:
    Specify the template parameter for AlphaDynInst
base/traceflags.py:
    Add load store queue, store set, and mem dependence unit to the
    list of trace flags.
cpu/base_dyn_inst.cc:
    Change formating, add in debug statement.
cpu/base_dyn_inst.hh:
    Change DynInst to be RefCounted, add flag to clear whether or not this
    instruction can commit.  This is likely to be removed in the future.
cpu/beta_cpu/alpha_dyn_inst.cc:
    AlphaDynInst has been changed to be templated, so now this CC file
    is just used to force instantiations of AlphaDynInst.
cpu/beta_cpu/alpha_dyn_inst.hh:
    Changed AlphaDynInst to be templated on Impl.  Removed some unnecessary
    functions.
cpu/beta_cpu/alpha_full_cpu.cc:
    AlphaFullCPU has been changed to be templated, so this CC file is now
    just used to force instantation of AlphaFullCPU.
cpu/beta_cpu/alpha_full_cpu.hh:
    Change AlphaFullCPU to be templated on Impl.
cpu/beta_cpu/alpha_impl.hh:
    Update it to reflect AlphaDynInst and AlphaFullCPU being templated
    on Impl.  Also removed time buffers from here, as they are really
    a part of the CPU and are thus in the CPU policy now.
cpu/beta_cpu/alpha_params.hh:
    Make AlphaSimpleParams inherit from the BaseFullCPU so that it doesn't
    need to specifically declare any parameters that are already in the
    BaseFullCPU.
cpu/beta_cpu/comm.hh:
    Changed the structure of the time buffer communication structs.  Now
    they include the size of the packet of instructions it is sending.
    Added some parameters to the backwards communication struct, mainly
    for squashing.
cpu/beta_cpu/commit.hh:
    Update typenames to reflect change in location of time buffer structs.
    Update DynInst to DynInstPtr (it is refcounted now).
cpu/beta_cpu/commit_impl.hh:
    Formatting changes mainly.  Also sends back proper information
    on branch mispredicts so that the bpred unit can update itself.
    Updated behavior for non-speculative instructions (stores, any
    other non-spec instructions): once they reach the head of the ROB,
    the ROB signals back to the IQ that it can go ahead and issue the
    non-speculative instruction.  The instruction itself is updated so that
    commit won't try to commit it again until it is done executing.
cpu/beta_cpu/cpu_policy.hh:
    Added branch prediction unit, mem dependence prediction unit, load
    store queue.  Moved time buffer structs from AlphaSimpleImpl to here.
cpu/beta_cpu/decode.hh:
    Changed typedefs to reflect change in location of time buffer structs
    and also the change from DynInst to ref counted DynInstPtr.
cpu/beta_cpu/decode_impl.hh:
    Continues to buffer instructions even while unblocking now.  Changed
    how it loops through groups of instructions so it can properly block
    during the middle of a group of instructions.
cpu/beta_cpu/fetch.hh:
    Changed typedefs to reflect change in location of time buffer structs
    and the change to ref counted DynInsts.  Also added in branch
    brediction unit.
cpu/beta_cpu/fetch_impl.hh:
    Add in branch prediction.  Changed how fetch checks inputs and its
    current state to make for easier logic.
cpu/beta_cpu/free_list.cc:
    Changed int regs and float regs to logically use one flat namespace.
    Future change will be moving them to a single scoreboard to conserve
    space.
cpu/beta_cpu/free_list.hh:
    Mostly debugging statements.  Might be removed for performance in future.
cpu/beta_cpu/full_cpu.cc:
    Added in some debugging statements.  Updated BaseFullCPU to take
    a params object.
cpu/beta_cpu/full_cpu.hh:
    Added params class within BaseCPU that other param classes will be
    able to inherit from.  Updated typedefs to reflect change in location
    of time buffer structs and ref counted DynInst.
cpu/beta_cpu/iew.hh:
    Updated typedefs to reflect change in location of time buffer structs
    and use of ref counted DynInsts.
cpu/beta_cpu/iew_impl.hh:
    Added in load store queue, updated iew to be able to execute non-
    speculative instructions, instead of having them execute in commit.
cpu/beta_cpu/inst_queue.hh:
    Updated change to ref counted DynInsts.  Changed inst queue to hold
    non-speculative instructions as well, which are issued only when
    commit signals backwards that a nonspeculative instruction is at
    the head of the ROB.
cpu/beta_cpu/inst_queue_impl.hh:
    Updated to allow for non-speculative instructions to be in the inst
    queue.  Also added some debug functions.
cpu/beta_cpu/regfile.hh:
    Added debugging statements, changed formatting.
cpu/beta_cpu/rename.hh:
    Updated typedefs, added some functions to clean up code.
cpu/beta_cpu/rename_impl.hh:
    Moved some code into functions to make it easier to read.
cpu/beta_cpu/rename_map.cc:
    Changed int and float reg behavior to use a single flat namespace.  In
    the future, the rename maps can be combined to a single rename map to
    save space.
cpu/beta_cpu/rename_map.hh:
    Added destructor.
cpu/beta_cpu/rob.hh:
    Updated it with change from DynInst to ref counted DynInst.
cpu/beta_cpu/rob_impl.hh:
    Formatting, updated to use ref counted DynInst.
cpu/static_inst.hh:
    Updated forward declaration for AlphaDynInst now that it is templated.

--HG--
extra : convert_revision : 1045f240ee9b6a4bd368e1806aca029ebbdc6dd3

1 files changed, 24 insertions, 21 deletions

diff --git a/cpu/beta_cpu/rename.hh b/cpu/beta_cpu/rename.hh
index cd66ce686..9f031012a 100644
--- a/cpu/beta_cpu/rename.hh
+++ b/cpu/beta_cpu/rename.hh
@@ -1,25 +1,14 @@
 // Todo:
-// Figure out rename map for reg vs fp (probably just have one rename map).
-// In simple case, there is no renaming, so have this stage do basically
-// nothing.
-// Fix up trap and barrier handling.  Fix up squashing too, as it's too
-// dependent upon the iew stage continually telling it to squash.
-// Have commit send back information whenever a branch has committed.  This
-// way the history buffer can be cleared beyond the point where the branch
-// was.
+// Fix up trap and barrier handling.
+// May want to have different statuses to differentiate the different stall
+// conditions.
 
 #ifndef __SIMPLE_RENAME_HH__
 #define __SIMPLE_RENAME_HH__
 
-//Will want to include: time buffer, structs, free list, rename map
 #include <list>
 
 #include "base/timebuf.hh"
-#include "cpu/beta_cpu/comm.hh"
-#include "cpu/beta_cpu/rename_map.hh"
-#include "cpu/beta_cpu/free_list.hh"
-
-using namespace std;
 
 // Will need rename maps for both the int reg file and fp reg file.
 // Or change rename map class to handle both. (RegFile handles both.)
@@ -30,14 +19,14 @@ class SimpleRename
     // Typedefs from the Impl.
     typedef typename Impl::ISA ISA;
     typedef typename Impl::CPUPol CPUPol;
-    typedef typename Impl::DynInst DynInst;
+    typedef typename Impl::DynInstPtr DynInstPtr;
     typedef typename Impl::FullCPU FullCPU;
     typedef typename Impl::Params Params;
 
-    typedef typename Impl::FetchStruct FetchStruct;
-    typedef typename Impl::DecodeStruct DecodeStruct;
-    typedef typename Impl::RenameStruct RenameStruct;
-    typedef typename Impl::TimeStruct TimeStruct;
+    typedef typename CPUPol::FetchStruct FetchStruct;
+    typedef typename CPUPol::DecodeStruct DecodeStruct;
+    typedef typename CPUPol::RenameStruct RenameStruct;
+    typedef typename CPUPol::TimeStruct TimeStruct;
 
     // Typedefs from the CPUPol
     typedef typename CPUPol::FreeList FreeList;
@@ -94,6 +83,14 @@ class SimpleRename
 
     void removeFromHistory(InstSeqNum inst_seq_num);
 
+    inline void renameSrcRegs(DynInstPtr &inst);
+
+    inline void renameDestRegs(DynInstPtr &inst);
+
+    inline int calcFreeROBEntries();
+
+    inline int calcFreeIQEntries();
+
     /** Holds the previous information for each rename.
      *  Note that often times the inst may have been deleted, so only access
      *  the pointer for the address and do not dereference it.
@@ -123,7 +120,7 @@ class SimpleRename
         bool placeHolder;
     };
 
-    list<RenameHistory> historyBuffer;
+    std::list<RenameHistory> historyBuffer;
 
     /** CPU interface. */
     FullCPU *cpu;
@@ -155,7 +152,7 @@ class SimpleRename
     typename TimeBuffer<DecodeStruct>::wire fromDecode;
 
     /** Skid buffer between rename and decode. */
-    queue<DecodeStruct> skidBuffer;
+    std::queue<DecodeStruct> skidBuffer;
 
     /** Rename map interface. */
     SimpleRenameMap *renameMap;
@@ -179,6 +176,12 @@ class SimpleRename
      *  instructions might have freed registers in the previous cycle.
      */
     unsigned commitWidth;
+
+    /** The instruction that rename is currently on.  It needs to have
+     *  persistent state so that when a stall occurs in the middle of a
+     *  group of instructions, it can restart at the proper instruction.
+     */
+    unsigned numInst;
 };
 
 #endif // __SIMPLE_RENAME_HH__