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authorKevin Lim <ktlim@umich.edu>2005-05-19 01:28:25 -0400
committerKevin Lim <ktlim@umich.edu>2005-05-19 01:28:25 -0400
commitc2fcac7c0dd8dff182cb262bdf35d5c67117aa42 (patch)
treefc8804bfbe1aa820c8afa446622b9ec8c658b75e /cpu/beta_cpu/rename_impl.hh
parente5721ce6777726fa54aee49be414233656bd98d1 (diff)
downloadgem5-c2fcac7c0dd8dff182cb262bdf35d5c67117aa42.tar.xz
Fix up code for initial release. The main bug that remains is properly forwarding data from stores to loads, specifically when they are of differing sizes.
cpu/base_dyn_inst.cc: Remove unused commented out code. cpu/base_dyn_inst.hh: Fix up comments. cpu/beta_cpu/2bit_local_pred.cc: Reorder code to match header file. cpu/beta_cpu/2bit_local_pred.hh: Update comments. cpu/beta_cpu/alpha_dyn_inst.hh: Remove useless comments. cpu/beta_cpu/alpha_dyn_inst_impl.hh: cpu/beta_cpu/alpha_full_cpu_impl.hh: cpu/beta_cpu/comm.hh: cpu/beta_cpu/iew_impl.hh: Remove unused commented code. cpu/beta_cpu/alpha_full_cpu.hh: Remove obsolete comment. cpu/beta_cpu/alpha_impl.hh: cpu/beta_cpu/full_cpu.hh: Alphabetize includes. cpu/beta_cpu/bpred_unit.hh: Remove unused global history code. cpu/beta_cpu/btb.hh: cpu/beta_cpu/free_list.hh: Use full path in #defines. cpu/beta_cpu/commit.hh: cpu/beta_cpu/decode.hh: Reorder functions. cpu/beta_cpu/commit_impl.hh: Remove obsolete commented code. cpu/beta_cpu/fetch.hh: Remove obsolete comments. cpu/beta_cpu/fetch_impl.hh: cpu/beta_cpu/rename_impl.hh: Remove commented code. cpu/beta_cpu/full_cpu.cc: Remove useless defines. cpu/beta_cpu/inst_queue.hh: Use full path for #defines. cpu/beta_cpu/inst_queue_impl.hh: Reorder functions to match header file. cpu/beta_cpu/mem_dep_unit.hh: Use full path name for #defines. cpu/beta_cpu/ras.hh: Use full path names for #defines. Remove mod operation. cpu/beta_cpu/regfile.hh: Remove unused commented code, fix up current comments. cpu/beta_cpu/tournament_pred.cc: cpu/beta_cpu/tournament_pred.hh: Update programming style. --HG-- extra : convert_revision : fb9d18a853f58a1108ff827e3c123d5b52a0608a
Diffstat (limited to 'cpu/beta_cpu/rename_impl.hh')
-rw-r--r--cpu/beta_cpu/rename_impl.hh20
1 files changed, 1 insertions, 19 deletions
diff --git a/cpu/beta_cpu/rename_impl.hh b/cpu/beta_cpu/rename_impl.hh
index 5a8e499e9..5ad0d1416 100644
--- a/cpu/beta_cpu/rename_impl.hh
+++ b/cpu/beta_cpu/rename_impl.hh
@@ -507,6 +507,7 @@ SimpleRename<Impl>::tick()
DPRINTF(Rename, "Rename: Done squashing, going to running.\n");
_status = Running;
+ rename();
} else {
doSquash();
}
@@ -523,25 +524,6 @@ SimpleRename<Impl>::tick()
#endif
}
- // Perhaps put this outside of this function, since this will
- // happen regardless of whether or not the stage is blocked or
- // squashing.
- // Read from the time buffer any necessary data.
- // Read registers that are freed, and add them to the freelist.
- // This is unnecessary due to the history buffer (assuming the history
- // buffer works properly).
-/*
- while(!fromCommit->commitInfo.freeRegs.empty())
- {
- PhysRegIndex freed_reg = fromCommit->commitInfo.freeRegs.back();
- DPRINTF(Rename, "Rename: Adding freed register %i to freelist.\n",
- (int)freed_reg);
- freeList->addReg(freed_reg);
-
- fromCommit->commitInfo.freeRegs.pop_back();
- }
-*/
-
}
template<class Impl>