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authorNathan Binkert <binkertn@umich.edu>2005-06-04 20:50:10 -0400
committerNathan Binkert <binkertn@umich.edu>2005-06-04 20:50:10 -0400
commit13c005a8af79a8481879ce099b45a1f98faae165 (patch)
tree3125dfe10539270433981b39119dd727295c255c /cpu/beta_cpu/store_set.cc
parent5a94e6f2cc6ed8480063da68d20274ced2930925 (diff)
downloadgem5-13c005a8af79a8481879ce099b45a1f98faae165.tar.xz
shuffle files around for new directory structure
--HG-- rename : cpu/base_cpu.cc => cpu/base.cc rename : cpu/base_cpu.hh => cpu/base.hh rename : cpu/beta_cpu/2bit_local_pred.cc => cpu/o3/2bit_local_pred.cc rename : cpu/beta_cpu/2bit_local_pred.hh => cpu/o3/2bit_local_pred.hh rename : cpu/beta_cpu/alpha_full_cpu.cc => cpu/o3/alpha_cpu.cc rename : cpu/beta_cpu/alpha_full_cpu.hh => cpu/o3/alpha_cpu.hh rename : cpu/beta_cpu/alpha_full_cpu_builder.cc => cpu/o3/alpha_cpu_builder.cc rename : cpu/beta_cpu/alpha_full_cpu_impl.hh => cpu/o3/alpha_cpu_impl.hh rename : cpu/beta_cpu/alpha_dyn_inst.cc => cpu/o3/alpha_dyn_inst.cc rename : cpu/beta_cpu/alpha_dyn_inst.hh => cpu/o3/alpha_dyn_inst.hh rename : cpu/beta_cpu/alpha_dyn_inst_impl.hh => cpu/o3/alpha_dyn_inst_impl.hh rename : cpu/beta_cpu/alpha_impl.hh => cpu/o3/alpha_impl.hh rename : cpu/beta_cpu/alpha_params.hh => cpu/o3/alpha_params.hh rename : cpu/beta_cpu/bpred_unit.cc => cpu/o3/bpred_unit.cc rename : cpu/beta_cpu/bpred_unit.hh => cpu/o3/bpred_unit.hh rename : cpu/beta_cpu/bpred_unit_impl.hh => cpu/o3/bpred_unit_impl.hh rename : cpu/beta_cpu/btb.cc => cpu/o3/btb.cc rename : cpu/beta_cpu/btb.hh => cpu/o3/btb.hh rename : cpu/beta_cpu/comm.hh => cpu/o3/comm.hh rename : cpu/beta_cpu/commit.cc => cpu/o3/commit.cc rename : cpu/beta_cpu/commit.hh => cpu/o3/commit.hh rename : cpu/beta_cpu/commit_impl.hh => cpu/o3/commit_impl.hh rename : cpu/beta_cpu/full_cpu.cc => cpu/o3/cpu.cc rename : cpu/beta_cpu/full_cpu.hh => cpu/o3/cpu.hh rename : cpu/beta_cpu/cpu_policy.hh => cpu/o3/cpu_policy.hh rename : cpu/beta_cpu/decode.cc => cpu/o3/decode.cc rename : cpu/beta_cpu/decode.hh => cpu/o3/decode.hh rename : cpu/beta_cpu/decode_impl.hh => cpu/o3/decode_impl.hh rename : cpu/beta_cpu/fetch.cc => cpu/o3/fetch.cc rename : cpu/beta_cpu/fetch.hh => cpu/o3/fetch.hh rename : cpu/beta_cpu/fetch_impl.hh => cpu/o3/fetch_impl.hh rename : cpu/beta_cpu/free_list.cc => cpu/o3/free_list.cc rename : cpu/beta_cpu/free_list.hh => cpu/o3/free_list.hh rename : cpu/beta_cpu/iew.cc => cpu/o3/iew.cc rename : cpu/beta_cpu/iew.hh => cpu/o3/iew.hh rename : cpu/beta_cpu/iew_impl.hh => cpu/o3/iew_impl.hh rename : cpu/beta_cpu/inst_queue.cc => cpu/o3/inst_queue.cc rename : cpu/beta_cpu/inst_queue.hh => cpu/o3/inst_queue.hh rename : cpu/beta_cpu/inst_queue_impl.hh => cpu/o3/inst_queue_impl.hh rename : cpu/beta_cpu/mem_dep_unit.cc => cpu/o3/mem_dep_unit.cc rename : cpu/beta_cpu/mem_dep_unit.hh => cpu/o3/mem_dep_unit.hh rename : cpu/beta_cpu/mem_dep_unit_impl.hh => cpu/o3/mem_dep_unit_impl.hh rename : cpu/beta_cpu/ras.cc => cpu/o3/ras.cc rename : cpu/beta_cpu/ras.hh => cpu/o3/ras.hh rename : cpu/beta_cpu/regfile.hh => cpu/o3/regfile.hh rename : cpu/beta_cpu/rename.cc => cpu/o3/rename.cc rename : cpu/beta_cpu/rename.hh => cpu/o3/rename.hh rename : cpu/beta_cpu/rename_impl.hh => cpu/o3/rename_impl.hh rename : cpu/beta_cpu/rename_map.cc => cpu/o3/rename_map.cc rename : cpu/beta_cpu/rename_map.hh => cpu/o3/rename_map.hh rename : cpu/beta_cpu/rob.cc => cpu/o3/rob.cc rename : cpu/beta_cpu/rob.hh => cpu/o3/rob.hh rename : cpu/beta_cpu/rob_impl.hh => cpu/o3/rob_impl.hh rename : cpu/beta_cpu/sat_counter.cc => cpu/o3/sat_counter.cc rename : cpu/beta_cpu/sat_counter.hh => cpu/o3/sat_counter.hh rename : cpu/beta_cpu/store_set.cc => cpu/o3/store_set.cc rename : cpu/beta_cpu/store_set.hh => cpu/o3/store_set.hh rename : cpu/beta_cpu/tournament_pred.cc => cpu/o3/tournament_pred.cc rename : cpu/beta_cpu/tournament_pred.hh => cpu/o3/tournament_pred.hh rename : cpu/ooo_cpu/ooo_cpu.cc => cpu/ozone/cpu.cc rename : cpu/ooo_cpu/ooo_cpu.hh => cpu/ozone/cpu.hh rename : cpu/ooo_cpu/ooo_impl.hh => cpu/ozone/cpu_impl.hh rename : cpu/ooo_cpu/ea_list.cc => cpu/ozone/ea_list.cc rename : cpu/ooo_cpu/ea_list.hh => cpu/ozone/ea_list.hh rename : cpu/simple_cpu/simple_cpu.cc => cpu/simple/cpu.cc rename : cpu/simple_cpu/simple_cpu.hh => cpu/simple/cpu.hh rename : cpu/full_cpu/smt.hh => cpu/smt.hh rename : cpu/full_cpu/op_class.hh => encumbered/cpu/full/op_class.hh extra : convert_revision : c4a891d8d6d3e0e9e5ea56be47d851da44d8c032
Diffstat (limited to 'cpu/beta_cpu/store_set.cc')
-rw-r--r--cpu/beta_cpu/store_set.cc282
1 files changed, 0 insertions, 282 deletions
diff --git a/cpu/beta_cpu/store_set.cc b/cpu/beta_cpu/store_set.cc
deleted file mode 100644
index 8b9a20c02..000000000
--- a/cpu/beta_cpu/store_set.cc
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "base/trace.hh"
-#include "cpu/beta_cpu/store_set.hh"
-
-StoreSet::StoreSet(int _SSIT_size, int _LFST_size)
- : SSIT_size(_SSIT_size), LFST_size(_LFST_size)
-{
- DPRINTF(StoreSet, "StoreSet: Creating store set object.\n");
- DPRINTF(StoreSet, "StoreSet: SSIT size: %i, LFST size: %i.\n",
- SSIT_size, LFST_size);
-
- SSIT = new SSID[SSIT_size];
-
- validSSIT.resize(SSIT_size);
-
- for (int i = 0; i < SSIT_size; ++i)
- validSSIT[i] = false;
-
- LFST = new InstSeqNum[LFST_size];
-
- validLFST.resize(LFST_size);
-
- SSCounters = new int[LFST_size];
-
- for (int i = 0; i < LFST_size; ++i)
- {
- validLFST[i] = false;
- SSCounters[i] = 0;
- }
-
- index_mask = SSIT_size - 1;
-
- offset_bits = 2;
-}
-
-void
-StoreSet::violation(Addr store_PC, Addr load_PC)
-{
- int load_index = calcIndex(load_PC);
- int store_index = calcIndex(store_PC);
-
- assert(load_index < SSIT_size && store_index < SSIT_size);
-
- bool valid_load_SSID = validSSIT[load_index];
- bool valid_store_SSID = validSSIT[store_index];
-
- if (!valid_load_SSID && !valid_store_SSID) {
- // Calculate a new SSID here.
- SSID new_set = calcSSID(load_PC);
-
- validSSIT[load_index] = true;
-
- SSIT[load_index] = new_set;
-
- validSSIT[store_index] = true;
-
- SSIT[store_index] = new_set;
-
- assert(new_set < LFST_size);
-
- SSCounters[new_set]++;
-
-
- DPRINTF(StoreSet, "StoreSet: Neither load nor store had a valid "
- "storeset, creating a new one: %i for load %#x, store %#x\n",
- new_set, load_PC, store_PC);
- } else if (valid_load_SSID && !valid_store_SSID) {
- SSID load_SSID = SSIT[load_index];
-
- validSSIT[store_index] = true;
-
- SSIT[store_index] = load_SSID;
-
- assert(load_SSID < LFST_size);
-
- SSCounters[load_SSID]++;
-
- DPRINTF(StoreSet, "StoreSet: Load had a valid store set. Adding "
- "store to that set: %i for load %#x, store %#x\n",
- load_SSID, load_PC, store_PC);
- } else if (!valid_load_SSID && valid_store_SSID) {
- SSID store_SSID = SSIT[store_index];
-
- validSSIT[load_index] = true;
-
- SSIT[load_index] = store_SSID;
-
- // Because we are having a load point to an already existing set,
- // the size of the store set is not incremented.
-
- DPRINTF(StoreSet, "StoreSet: Store had a valid store set: %i for "
- "load %#x, store %#x\n",
- store_SSID, load_PC, store_PC);
- } else {
- SSID load_SSID = SSIT[load_index];
- SSID store_SSID = SSIT[store_index];
-
- assert(load_SSID < LFST_size && store_SSID < LFST_size);
-
- int load_SS_size = SSCounters[load_SSID];
- int store_SS_size = SSCounters[store_SSID];
-
- // If the load has the bigger store set, then assign the store
- // to the same store set as the load. Otherwise vice-versa.
- if (load_SS_size > store_SS_size) {
- SSIT[store_index] = load_SSID;
-
- SSCounters[load_SSID]++;
- SSCounters[store_SSID]--;
-
- DPRINTF(StoreSet, "StoreSet: Load had bigger store set: %i; "
- "for load %#x, store %#x\n",
- load_SSID, load_PC, store_PC);
- } else {
- SSIT[load_index] = store_SSID;
-
- SSCounters[store_SSID]++;
- SSCounters[load_SSID]--;
-
- DPRINTF(StoreSet, "StoreSet: Store had bigger store set: %i; "
- "for load %#x, store %#x\n",
- store_SSID, load_PC, store_PC);
- }
- }
-}
-
-void
-StoreSet::insertLoad(Addr load_PC, InstSeqNum load_seq_num)
-{
- // Does nothing.
- return;
-}
-
-void
-StoreSet::insertStore(Addr store_PC, InstSeqNum store_seq_num)
-{
- int index = calcIndex(store_PC);
-
- int store_SSID;
-
- assert(index < SSIT_size);
-
- if (!validSSIT[index]) {
- // Do nothing if there's no valid entry.
- return;
- } else {
- store_SSID = SSIT[index];
-
- assert(store_SSID < LFST_size);
-
- // Update the last store that was fetched with the current one.
- LFST[store_SSID] = store_seq_num;
-
- validLFST[store_SSID] = 1;
-
- DPRINTF(StoreSet, "Store %#x updated the LFST, SSID: %i\n",
- store_PC, store_SSID);
- }
-}
-
-InstSeqNum
-StoreSet::checkInst(Addr PC)
-{
- int index = calcIndex(PC);
-
- int inst_SSID;
-
- assert(index < SSIT_size);
-
- if (!validSSIT[index]) {
- DPRINTF(StoreSet, "Inst %#x with index %i had no SSID\n",
- PC, index);
-
- // Return 0 if there's no valid entry.
- return 0;
- } else {
- inst_SSID = SSIT[index];
-
- assert(inst_SSID < LFST_size);
-
- if (!validLFST[inst_SSID]) {
-
- DPRINTF(StoreSet, "Inst %#x with index %i and SSID %i had no "
- "dependency\n", PC, index, inst_SSID);
-
- return 0;
- } else {
- DPRINTF(StoreSet, "Inst %#x with index %i and SSID %i had LFST "
- "inum of %i\n", PC, index, inst_SSID, LFST[inst_SSID]);
-
- return LFST[inst_SSID];
- }
- }
-}
-
-void
-StoreSet::issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store)
-{
- // This only is updated upon a store being issued.
- if (!is_store) {
- return;
- }
-
- int index = calcIndex(issued_PC);
-
- int store_SSID;
-
- assert(index < SSIT_size);
-
- // Make sure the SSIT still has a valid entry for the issued store.
- if (!validSSIT[index]) {
- return;
- }
-
- store_SSID = SSIT[index];
-
- assert(store_SSID < LFST_size);
-
- // If the last fetched store in the store set refers to the store that
- // was just issued, then invalidate the entry.
- if (validLFST[store_SSID] && LFST[store_SSID] == issued_seq_num) {
- DPRINTF(StoreSet, "StoreSet: store invalidated itself in LFST.\n");
- validLFST[store_SSID] = false;
- }
-}
-
-void
-StoreSet::squash(InstSeqNum squashed_num)
-{
- // Not really sure how to do this well.
- // Generally this is small enough that it should be okay; short circuit
- // evaluation should take care of invalid entries.
-
- DPRINTF(StoreSet, "StoreSet: Squashing until inum %i\n",
- squashed_num);
-
- for (int i = 0; i < LFST_size; ++i) {
- if (validLFST[i] && LFST[i] < squashed_num) {
- validLFST[i] = false;
- }
- }
-}
-
-void
-StoreSet::clear()
-{
- for (int i = 0; i < SSIT_size; ++i) {
- validSSIT[i] = false;
- }
-
- for (int i = 0; i < LFST_size; ++i) {
- validLFST[i] = false;
- }
-}
-