Initial light-weight OoO CPU checkin, along with gcc-3.4 fixes.

SConscript:
    Include new files.
arch/alpha/isa_desc:
    Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them.
arch/alpha/isa_traits.hh:
    Add enum for total number of data registers.
arch/isa_parser.py:
base/traceflags.py:
    Include new light-weight OoO CPU model.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
    Changes to abstract more away from the base dyn inst class.
cpu/beta_cpu/2bit_local_pred.cc:
cpu/beta_cpu/2bit_local_pred.hh:
cpu/beta_cpu/tournament_pred.cc:
cpu/beta_cpu/tournament_pred.hh:
    Remove redundant SatCounter class.
cpu/beta_cpu/alpha_dyn_inst.cc:
cpu/beta_cpu/alpha_full_cpu.cc:
cpu/beta_cpu/alpha_full_cpu.hh:
cpu/beta_cpu/bpred_unit.cc:
cpu/beta_cpu/inst_queue.cc:
cpu/beta_cpu/mem_dep_unit.cc:
cpu/beta_cpu/ras.cc:
cpu/beta_cpu/rename_map.cc:
cpu/beta_cpu/rename_map.hh:
cpu/beta_cpu/rob.cc:
    Fix for gcc-3.4
cpu/beta_cpu/alpha_dyn_inst.hh:
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
    Fixes for gcc-3.4.
    Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
    Make params match the current params inherited from BaseCPU.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
    Fixes for gcc-3.4
cpu/beta_cpu/full_cpu.cc:
    Use new params pointer in BaseCPU.
    Fix for gcc-3.4.
cpu/beta_cpu/full_cpu.hh:
    Use new params class from BaseCPU.
cpu/beta_cpu/iew_impl.hh:
    Remove unused function.
cpu/simple_cpu/simple_cpu.cc:
    Remove unused global variable.
cpu/static_inst.hh:
    Include OoODynInst for new lightweight OoO CPU

--HG--
extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa

23 files changed, 410 insertions, 302 deletions

diff --git a/cpu/beta_cpu/2bit_local_pred.cc b/cpu/beta_cpu/2bit_local_pred.cc
index ef7f23d49..e5bf9647f 100644
--- a/cpu/beta_cpu/2bit_local_pred.cc
+++ b/cpu/beta_cpu/2bit_local_pred.cc
@@ -1,36 +1,6 @@
 #include "base/trace.hh"
 #include "cpu/beta_cpu/2bit_local_pred.hh"
 
-DefaultBP::SatCounter::SatCounter(unsigned bits)
-    : maxVal((1 << bits) - 1), counter(0)
-{
-}
-
-DefaultBP::SatCounter::SatCounter(unsigned bits, unsigned initial_val)
-    : maxVal((1 << bits) - 1), counter(initial_val)
-{
-    // Check to make sure initial value doesn't exceed the max counter value.
-    if (initial_val > maxVal) {
-        panic("BP: Initial counter value exceeds max size.");
-    }
-}
-
-void
-DefaultBP::SatCounter::increment()
-{
-    if(counter < maxVal) {
-        ++counter;
-    }
-}
-
-void
-DefaultBP::SatCounter::decrement()
-{
-    if(counter > 0) {
-        --counter;
-    }
-}
-
 DefaultBP::DefaultBP(unsigned _localPredictorSize,
                      unsigned _localCtrBits,
                      unsigned _instShiftAmt)
@@ -46,7 +16,10 @@ DefaultBP::DefaultBP(unsigned _localPredictorSize,
     DPRINTF(Fetch, "Branch predictor: index mask: %#x\n", indexMask);
 
     // Setup the array of counters for the local predictor.
-    localCtrs = new SatCounter[localPredictorSize](localCtrBits);
+    localCtrs = new SatCounter[localPredictorSize];
+
+    for (int i = 0; i < localPredictorSize; ++i)
+        localCtrs[i].setBits(_localCtrBits);
 
     DPRINTF(Fetch, "Branch predictor: local predictor size: %i\n",
             localPredictorSize);
diff --git a/cpu/beta_cpu/2bit_local_pred.hh b/cpu/beta_cpu/2bit_local_pred.hh
index 32a7972d0..cda7d3e65 100644
--- a/cpu/beta_cpu/2bit_local_pred.hh
+++ b/cpu/beta_cpu/2bit_local_pred.hh
@@ -1,8 +1,9 @@
-#ifndef __2BIT_LOCAL_PRED_HH__
-#define __2BIT_LOCAL_PRED_HH__
+#ifndef __CPU_BETA_CPU_2BIT_LOCAL_PRED_HH__
+#define __CPU_BETA_CPU_2BIT_LOCAL_PRED_HH__
 
 // For Addr type.
 #include "arch/alpha/isa_traits.hh"
+#include "cpu/beta_cpu/sat_counter.hh"
 
 class DefaultBP
 {
@@ -34,52 +35,6 @@ class DefaultBP
 
     inline unsigned getLocalIndex(Addr &PC);
 
-    /**
-     * Private counter class for the internal saturating counters.
-     * Implements an n bit saturating counter and provides methods to
-     * increment, decrement, and read it.
-     * @todo Consider making this something that more closely mimics a
-     * built in class so you can use ++ or --.
-     */
-    class SatCounter
-    {
-      public:
-        /**
-         * Constructor for the counter.
-         * @param bits How many bits the counter will have.
-         */
-        SatCounter(unsigned bits);
-
-        /**
-         * Constructor for the counter.
-         * @param bits How many bits the counter will have.
-         * @param initial_val Starting value for each counter.
-         */
-        SatCounter(unsigned bits, unsigned initial_val);
-
-        /**
-         * Increments the counter's current value.
-         */
-        void increment();
-
-        /**
-         * Decrements the counter's current value.
-         */
-        void decrement();
-
-        /**
-         * Read the counter's value.
-         */
-        uint8_t read()
-        {
-            return counter;
-        }
-
-      private:
-        uint8_t maxVal;
-        uint8_t counter;
-    };
-
     /** Array of counters that make up the local predictor. */
     SatCounter *localCtrs;
 
@@ -96,4 +51,4 @@ class DefaultBP
     unsigned indexMask;
 };
 
-#endif // __2BIT_LOCAL_PRED_HH__
+#endif // __CPU_BETA_CPU_2BIT_LOCAL_PRED_HH__
diff --git a/cpu/beta_cpu/alpha_dyn_inst.cc b/cpu/beta_cpu/alpha_dyn_inst.cc
index 1bfcb8420..d929da1cf 100644
--- a/cpu/beta_cpu/alpha_dyn_inst.cc
+++ b/cpu/beta_cpu/alpha_dyn_inst.cc
@@ -4,4 +4,4 @@
 
 // Force instantiation of AlphaDynInst for all the implementations that
 // are needed.
-template AlphaDynInst<AlphaSimpleImpl>;
+template class AlphaDynInst<AlphaSimpleImpl>;
diff --git a/cpu/beta_cpu/alpha_dyn_inst.hh b/cpu/beta_cpu/alpha_dyn_inst.hh
index 584e027d7..b2f0d703e 100644
--- a/cpu/beta_cpu/alpha_dyn_inst.hh
+++ b/cpu/beta_cpu/alpha_dyn_inst.hh
@@ -47,11 +47,11 @@ class AlphaDynInst : public BaseDynInst<Impl>
     /** BaseDynInst constructor given a static inst pointer. */
     AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst);
 
-    /** Executes the instruction. */
+    /** Executes the instruction.  Why the hell did I put this here? */
     Fault execute()
     {
-        fault = staticInst->execute(this, traceData);
-        return fault;
+        this->fault = this->staticInst->execute(this, this->traceData);
+        return this->fault;
     }
 
   public:
@@ -74,6 +74,135 @@ class AlphaDynInst : public BaseDynInst<Impl>
     void syscall();
 #endif
 
+
+
+  private:
+    /** Physical register index of the destination registers of this
+     *  instruction.
+     */
+    PhysRegIndex _destRegIdx[MaxInstDestRegs];
+
+    /** Physical register index of the source registers of this
+     *  instruction.
+     */
+    PhysRegIndex _srcRegIdx[MaxInstSrcRegs];
+
+    /** Physical register index of the previous producers of the
+     *  architected destinations.
+     */
+    PhysRegIndex _prevDestRegIdx[MaxInstDestRegs];
+
+  public:
+
+    // The register accessor methods provide the index of the
+    // instruction's operand (e.g., 0 or 1), not the architectural
+    // register index, to simplify the implementation of register
+    // renaming.  We find the architectural register index by indexing
+    // into the instruction's own operand index table.  Note that a
+    // raw pointer to the StaticInst is provided instead of a
+    // ref-counted StaticInstPtr to redice overhead.  This is fine as
+    // long as these methods don't copy the pointer into any long-term
+    // storage (which is pretty hard to imagine they would have reason
+    // to do).
+
+    uint64_t readIntReg(StaticInst<ISA> *si, int idx)
+    {
+        return this->cpu->readIntReg(_srcRegIdx[idx]);
+    }
+
+    float readFloatRegSingle(StaticInst<ISA> *si, int idx)
+    {
+        return this->cpu->readFloatRegSingle(_srcRegIdx[idx]);
+    }
+
+    double readFloatRegDouble(StaticInst<ISA> *si, int idx)
+    {
+        return this->cpu->readFloatRegDouble(_srcRegIdx[idx]);
+    }
+
+    uint64_t readFloatRegInt(StaticInst<ISA> *si, int idx)
+    {
+        return this->cpu->readFloatRegInt(_srcRegIdx[idx]);
+    }
+    /** @todo: Make results into arrays so they can handle multiple dest
+     *  registers.
+     */
+    void setIntReg(StaticInst<ISA> *si, int idx, uint64_t val)
+    {
+        this->cpu->setIntReg(_destRegIdx[idx], val);
+        this->instResult.integer = val;
+    }
+
+    void setFloatRegSingle(StaticInst<ISA> *si, int idx, float val)
+    {
+        this->cpu->setFloatRegSingle(_destRegIdx[idx], val);
+        this->instResult.fp = val;
+    }
+
+    void setFloatRegDouble(StaticInst<ISA> *si, int idx, double val)
+    {
+        this->cpu->setFloatRegDouble(_destRegIdx[idx], val);
+        this->instResult.dbl = val;
+    }
+
+    void setFloatRegInt(StaticInst<ISA> *si, int idx, uint64_t val)
+    {
+        this->cpu->setFloatRegInt(_destRegIdx[idx], val);
+        this->instResult.integer = val;
+    }
+
+    /** Returns the physical register index of the i'th destination
+     *  register.
+     */
+    PhysRegIndex renamedDestRegIdx(int idx) const
+    {
+        return _destRegIdx[idx];
+    }
+
+    /** Returns the physical register index of the i'th source register. */
+    PhysRegIndex renamedSrcRegIdx(int idx) const
+    {
+        return _srcRegIdx[idx];
+    }
+
+    /** Returns the physical register index of the previous physical register
+     *  that remapped to the same logical register index.
+     */
+    PhysRegIndex prevDestRegIdx(int idx) const
+    {
+        return _prevDestRegIdx[idx];
+    }
+
+    /** Renames a destination register to a physical register.  Also records
+     *  the previous physical register that the logical register mapped to.
+     */
+    void renameDestReg(int idx,
+                       PhysRegIndex renamed_dest,
+                       PhysRegIndex previous_rename)
+    {
+        _destRegIdx[idx] = renamed_dest;
+        _prevDestRegIdx[idx] = previous_rename;
+    }
+
+    /** Renames a source logical register to the physical register which
+     *  has/will produce that logical register's result.
+     *  @todo: add in whether or not the source register is ready.
+     */
+    void renameSrcReg(int idx, PhysRegIndex renamed_src)
+    {
+        _srcRegIdx[idx] = renamed_src;
+    }
+
+  public:
+    Fault calcEA()
+    {
+        return this->staticInst->eaCompInst()->execute(this, this->traceData);
+    }
+
+    Fault memAccess()
+    {
+        return this->staticInst->memAccInst()->execute(this, this->traceData);
+    }
 };
 
 #endif // __CPU_BETA_CPU_ALPHA_DYN_INST_HH__
diff --git a/cpu/beta_cpu/alpha_dyn_inst_impl.hh b/cpu/beta_cpu/alpha_dyn_inst_impl.hh
index 8311067db..4a3ae99d4 100644
--- a/cpu/beta_cpu/alpha_dyn_inst_impl.hh
+++ b/cpu/beta_cpu/alpha_dyn_inst_impl.hh
@@ -4,42 +4,68 @@
 template <class Impl>
 AlphaDynInst<Impl>::AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC,
                                  InstSeqNum seq_num, FullCPU *cpu)
-    : BaseDynInst<AlphaSimpleImpl>(inst, PC, Pred_PC, seq_num, cpu)
+    : BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
 {
+    // Make sure to have the renamed register entries set to the same
+    // as the normal register entries.  It will allow the IQ to work
+    // without any modifications.
+    for (int i = 0; i < this->staticInst->numDestRegs(); i++)
+    {
+        _destRegIdx[i] = this->staticInst->destRegIdx(i);
+    }
+
+    for (int i = 0; i < this->staticInst->numSrcRegs(); i++)
+    {
+        _srcRegIdx[i] = this->staticInst->srcRegIdx(i);
+        this->_readySrcRegIdx[i] = 0;
+    }
+
 }
 
 template <class Impl>
 AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst)
-    : BaseDynInst<AlphaSimpleImpl>(_staticInst)
+    : BaseDynInst<Impl>(_staticInst)
 {
+    // Make sure to have the renamed register entries set to the same
+    // as the normal register entries.  It will allow the IQ to work
+    // without any modifications.
+    for (int i = 0; i < _staticInst->numDestRegs(); i++)
+    {
+        _destRegIdx[i] = _staticInst->destRegIdx(i);
+    }
+
+    for (int i = 0; i < _staticInst->numSrcRegs(); i++)
+    {
+        _srcRegIdx[i] = _staticInst->srcRegIdx(i);
+    }
 }
 
 template <class Impl>
 uint64_t
 AlphaDynInst<Impl>::readUniq()
 {
-    return cpu->readUniq();
+    return this->cpu->readUniq();
 }
 
 template <class Impl>
 void
 AlphaDynInst<Impl>::setUniq(uint64_t val)
 {
-    cpu->setUniq(val);
+    this->cpu->setUniq(val);
 }
 
 template <class Impl>
 uint64_t
 AlphaDynInst<Impl>::readFpcr()
 {
-    return cpu->readFpcr();
+    return this->cpu->readFpcr();
 }
 
 template <class Impl>
 void
 AlphaDynInst<Impl>::setFpcr(uint64_t val)
 {
-    cpu->setFpcr(val);
+    this->cpu->setFpcr(val);
 }
 
 #ifdef FULL_SYSTEM
@@ -47,63 +73,63 @@ template <class Impl>
 uint64_t
 AlphaDynInst<Impl>::readIpr(int idx, Fault &fault)
 {
-    return cpu->readIpr(idx, fault);
+    return this->cpu->readIpr(idx, fault);
 }
 
 template <class Impl>
 Fault
 AlphaDynInst<Impl>::setIpr(int idx, uint64_t val)
 {
-    return cpu->setIpr(idx, val);
+    return this->cpu->setIpr(idx, val);
 }
 
 template <class Impl>
 Fault
 AlphaDynInst<Impl>::hwrei()
 {
-    return cpu->hwrei();
+    return this->cpu->hwrei();
 }
 
 template <class Impl>
 int
 AlphaDynInst<Impl>::readIntrFlag()
 {
-return cpu->readIntrFlag();
+return this->cpu->readIntrFlag();
 }
 
 template <class Impl>
 void
 AlphaDynInst<Impl>::setIntrFlag(int val)
 {
-    cpu->setIntrFlag(val);
+    this->cpu->setIntrFlag(val);
 }
 
 template <class Impl>
 bool
 AlphaDynInst<Impl>::inPalMode()
 {
-    return cpu->inPalMode();
+    return this->cpu->inPalMode();
 }
 
 template <class Impl>
 void
 AlphaDynInst<Impl>::trap(Fault fault)
 {
-    cpu->trap(fault);
+    this->cpu->trap(fault);
 }
 
 template <class Impl>
 bool
 AlphaDynInst<Impl>::simPalCheck(int palFunc)
 {
-    return cpu->simPalCheck(palFunc);
+    return this->cpu->simPalCheck(palFunc);
 }
 #else
 template <class Impl>
 void
 AlphaDynInst<Impl>::syscall()
 {
-    cpu->syscall();
+    this->cpu->syscall();
 }
 #endif
 
diff --git a/cpu/beta_cpu/alpha_full_cpu.cc b/cpu/beta_cpu/alpha_full_cpu.cc
index 80c4bdec8..ee461eb13 100644
--- a/cpu/beta_cpu/alpha_full_cpu.cc
+++ b/cpu/beta_cpu/alpha_full_cpu.cc
@@ -6,4 +6,4 @@
 // Force instantiation of AlphaFullCPU for all the implemntations that are
 // needed.  Consider merging this and alpha_dyn_inst.cc, and maybe all
 // classes that depend on a certain impl, into one file (alpha_impl.cc?).
-template AlphaFullCPU<AlphaSimpleImpl>;
+template class AlphaFullCPU<AlphaSimpleImpl>;
diff --git a/cpu/beta_cpu/alpha_full_cpu.hh b/cpu/beta_cpu/alpha_full_cpu.hh
index 92eebc82a..3c29dd277 100644
--- a/cpu/beta_cpu/alpha_full_cpu.hh
+++ b/cpu/beta_cpu/alpha_full_cpu.hh
@@ -87,22 +87,22 @@ class AlphaFullCPU : public FullBetaCPU<Impl>
     // trying to rename source/destination registers...
     uint64_t readUniq()
     {
-        return regFile.readUniq();
+        return this->regFile.readUniq();
     }
 
     void setUniq(uint64_t val)
     {
-        regFile.setUniq(val);
+        this->regFile.setUniq(val);
     }
 
     uint64_t readFpcr()
     {
-        return regFile.readFpcr();
+        return this->regFile.readFpcr();
     }
 
     void setFpcr(uint64_t val)
     {
-        regFile.setFpcr(val);
+        this->regFile.setFpcr(val);
     }
 
 #ifdef FULL_SYSTEM
@@ -127,13 +127,13 @@ class AlphaFullCPU : public FullBetaCPU<Impl>
     // set the register.
     IntReg getSyscallArg(int i)
     {
-        return xc->regs.intRegFile[AlphaISA::ArgumentReg0 + i];
+        return this->xc->regs.intRegFile[AlphaISA::ArgumentReg0 + i];
     }
 
     // used to shift args for indirect syscall
     void setSyscallArg(int i, IntReg val)
     {
-        xc->regs.intRegFile[AlphaISA::ArgumentReg0 + i] = val;
+        this->xc->regs.intRegFile[AlphaISA::ArgumentReg0 + i] = val;
     }
 
     void setSyscallReturn(int64_t return_value)
@@ -144,12 +144,12 @@ class AlphaFullCPU : public FullBetaCPU<Impl>
         const int RegA3 = 19;	// only place this is used
         if (return_value >= 0) {
             // no error
-            xc->regs.intRegFile[RegA3] = 0;
-            xc->regs.intRegFile[AlphaISA::ReturnValueReg] = return_value;
+            this->xc->regs.intRegFile[RegA3] = 0;
+            this->xc->regs.intRegFile[AlphaISA::ReturnValueReg] = return_value;
         } else {
             // got an error, return details
-            xc->regs.intRegFile[RegA3] = (IntReg) -1;
-            xc->regs.intRegFile[AlphaISA::ReturnValueReg] = -return_value;
+            this->xc->regs.intRegFile[RegA3] = (IntReg) -1;
+            this->xc->regs.intRegFile[AlphaISA::ReturnValueReg] = -return_value;
         }
     }
 
@@ -188,7 +188,7 @@ class AlphaFullCPU : public FullBetaCPU<Impl>
 #endif
 
         Fault error;
-        error = mem->read(req, data);
+        error = this->mem->read(req, data);
         data = htoa(data);
         return error;
     }
@@ -203,7 +203,7 @@ class AlphaFullCPU : public FullBetaCPU<Impl>
 
         // If this is a store conditional, act appropriately
         if (req->flags & LOCKED) {
-            cregs = &xc->regs.miscRegs;
+            cregs = &this->xc->regs.miscRegs;
 
             if (req->flags & UNCACHEABLE) {
                 // Don't update result register (see stq_c in isa_desc)
@@ -241,7 +241,7 @@ class AlphaFullCPU : public FullBetaCPU<Impl>
 
 #endif
 
-        return mem->write(req, (T)htoa(data));
+        return this->mem->write(req, (T)htoa(data));
     }
 
 };
diff --git a/cpu/beta_cpu/alpha_full_cpu_builder.cc b/cpu/beta_cpu/alpha_full_cpu_builder.cc
index f37081232..cf9536cb8 100644
--- a/cpu/beta_cpu/alpha_full_cpu_builder.cc
+++ b/cpu/beta_cpu/alpha_full_cpu_builder.cc
@@ -283,10 +283,10 @@ CREATE_SIM_OBJECT(BaseFullCPU)
 
     params.mem = mem;
 
-    params.maxInstsAnyThread = max_insts_any_thread;
-    params.maxInstsAllThreads = max_insts_all_threads;
-    params.maxLoadsAnyThread = max_loads_any_thread;
-    params.maxLoadsAllThreads = max_loads_all_threads;
+    params.max_insts_any_thread = max_insts_any_thread;
+    params.max_insts_all_threads = max_insts_all_threads;
+    params.max_loads_any_thread = max_loads_any_thread;
+    params.max_loads_all_threads = max_loads_all_threads;
 
     //
     // Caches
diff --git a/cpu/beta_cpu/alpha_full_cpu_impl.hh b/cpu/beta_cpu/alpha_full_cpu_impl.hh
index 611a0d80d..fccded193 100644
--- a/cpu/beta_cpu/alpha_full_cpu_impl.hh
+++ b/cpu/beta_cpu/alpha_full_cpu_impl.hh
@@ -14,17 +14,17 @@
 
 template <class Impl>
 AlphaFullCPU<Impl>::AlphaFullCPU(Params &params)
-    : FullBetaCPU<AlphaSimpleImpl>(params)
+    : FullBetaCPU<Impl>(params)
 {
     DPRINTF(FullCPU, "AlphaFullCPU: Creating AlphaFullCPU object.\n");
 
-    fetch.setCPU(this);
-    decode.setCPU(this);
-    rename.setCPU(this);
-    iew.setCPU(this);
-    commit.setCPU(this);
+    this->fetch.setCPU(this);
+    this->decode.setCPU(this);
+    this->rename.setCPU(this);
+    this->iew.setCPU(this);
+    this->commit.setCPU(this);
 
-    rob.setCPU(this);
+    this->rob.setCPU(this);
 }
 
 template <class Impl>
@@ -32,12 +32,12 @@ void
 AlphaFullCPU<Impl>::regStats()
 {
     // Register stats for everything that has stats.
-    fullCPURegStats();
-    fetch.regStats();
-    decode.regStats();
-    rename.regStats();
-    iew.regStats();
-    commit.regStats();
+    this->fullCPURegStats();
+    this->fetch.regStats();
+    this->decode.regStats();
+    this->rename.regStats();
+    this->iew.regStats();
+    this->commit.regStats();
 }
 
 #ifndef FULL_SYSTEM
@@ -49,25 +49,25 @@ AlphaFullCPU<Impl>::syscall()
     DPRINTF(FullCPU, "AlphaFullCPU: Syscall() called.\n\n");
 
     // Commit stage needs to run as well.
-    commit.tick();
+    this->commit.tick();
 
     squashStages();
 
     // Temporarily increase this by one to account for the syscall
     // instruction.
-    ++funcExeInst;
+    ++(this->funcExeInst);
 
     // Copy over all important state to xc once all the unrolling is done.
     copyToXC();
 
-    process->syscall(xc);
+    this->process->syscall(this->xc);
 
     // Copy over all important state back to CPU.
     copyFromXC();
 
     // Decrease funcExeInst by one as the normal commit will handle
     // incrememnting it.
-    --funcExeInst;
+    --(this->funcExeInst);
 }
 
 // This is not a pretty function, and should only be used if it is necessary
@@ -77,40 +77,40 @@ template <class Impl>
 void
 AlphaFullCPU<Impl>::squashStages()
 {
-    InstSeqNum rob_head = rob.readHeadSeqNum();
+    InstSeqNum rob_head = this->rob.readHeadSeqNum();
 
     // Now hack the time buffer to put this sequence number in the places
     // where the stages might read it.
     for (int i = 0; i < 5; ++i)
     {
-        timeBuffer.access(-i)->commitInfo.doneSeqNum = rob_head;
+        this->timeBuffer.access(-i)->commitInfo.doneSeqNum = rob_head;
     }
 
-    fetch.squash(rob.readHeadNextPC());
-    fetchQueue.advance();
+    this->fetch.squash(this->rob.readHeadNextPC());
+    this->fetchQueue.advance();
 
-    decode.squash();
-    decodeQueue.advance();
+    this->decode.squash();
+    this->decodeQueue.advance();
 
-    rename.squash();
-    renameQueue.advance();
-    renameQueue.advance();
+    this->rename.squash();
+    this->renameQueue.advance();
+    this->renameQueue.advance();
 
     // Be sure to advance the IEW queues so that the commit stage doesn't
     // try to set an instruction as completed at the same time that it
     // might be deleting it.
-    iew.squash();
-    iewQueue.advance();
-    iewQueue.advance();
+    this->iew.squash();
+    this->iewQueue.advance();
+    this->iewQueue.advance();
 
-    rob.squash(rob_head);
-    commit.setSquashing();
+    this->rob.squash(rob_head);
+    this->commit.setSquashing();
 
     // Now hack the time buffer to clear the sequence numbers in the places
     // where the stages might read it.?
     for (int i = 0; i < 5; ++i)
     {
-        timeBuffer.access(-i)->commitInfo.doneSeqNum = 0;
+        this->timeBuffer.access(-i)->commitInfo.doneSeqNum = 0;
     }
 
 }
@@ -126,29 +126,31 @@ AlphaFullCPU<Impl>::copyToXC()
     // First loop through the integer registers.
     for (int i = 0; i < AlphaISA::NumIntRegs; ++i)
     {
-        renamed_reg = renameMap.lookup(i);
-        xc->regs.intRegFile[i] = regFile.readIntReg(renamed_reg);
+        renamed_reg = this->renameMap.lookup(i);
+        this->xc->regs.intRegFile[i] = this->regFile.readIntReg(renamed_reg);
         DPRINTF(FullCPU, "FullCPU: Copying register %i, has data %lli.\n",
-                renamed_reg, regFile.intRegFile[renamed_reg]);
+                renamed_reg, this->regFile.intRegFile[renamed_reg]);
     }
 
     // Then loop through the floating point registers.
     for (int i = 0; i < AlphaISA::NumFloatRegs; ++i)
     {
-        renamed_reg = renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
-        xc->regs.floatRegFile.d[i] = regFile.readFloatRegDouble(renamed_reg);
-        xc->regs.floatRegFile.q[i] = regFile.readFloatRegInt(renamed_reg);
+        renamed_reg = this->renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
+        this->xc->regs.floatRegFile.d[i] =
+            this->regFile.readFloatRegDouble(renamed_reg);
+        this->xc->regs.floatRegFile.q[i] =
+            this->regFile.readFloatRegInt(renamed_reg);
     }
 
-    xc->regs.miscRegs.fpcr = regFile.miscRegs.fpcr;
-    xc->regs.miscRegs.uniq = regFile.miscRegs.uniq;
-    xc->regs.miscRegs.lock_flag = regFile.miscRegs.lock_flag;
-    xc->regs.miscRegs.lock_addr = regFile.miscRegs.lock_addr;
+    this->xc->regs.miscRegs.fpcr = this->regFile.miscRegs.fpcr;
+    this->xc->regs.miscRegs.uniq = this->regFile.miscRegs.uniq;
+    this->xc->regs.miscRegs.lock_flag = this->regFile.miscRegs.lock_flag;
+    this->xc->regs.miscRegs.lock_addr = this->regFile.miscRegs.lock_addr;
 
-    xc->regs.pc = rob.readHeadPC();
-    xc->regs.npc = xc->regs.pc+4;
+    this->xc->regs.pc = this->rob.readHeadPC();
+    this->xc->regs.npc = this->xc->regs.pc+4;
 
-    xc->func_exe_inst = funcExeInst;
+    this->xc->func_exe_inst = this->funcExeInst;
 }
 
 // This function will probably mess things up unless the ROB is empty and
@@ -162,35 +164,37 @@ AlphaFullCPU<Impl>::copyFromXC()
     // First loop through the integer registers.
     for (int i = 0; i < AlphaISA::NumIntRegs; ++i)
     {
-        renamed_reg = renameMap.lookup(i);
+        renamed_reg = this->renameMap.lookup(i);
 
         DPRINTF(FullCPU, "FullCPU: Copying over register %i, had data %lli, "
                 "now has data %lli.\n",
-                renamed_reg, regFile.intRegFile[renamed_reg],
-                xc->regs.intRegFile[i]);
+                renamed_reg, this->regFile.intRegFile[renamed_reg],
+                this->xc->regs.intRegFile[i]);
 
-        regFile.setIntReg(renamed_reg, xc->regs.intRegFile[i]);
+        this->regFile.setIntReg(renamed_reg, this->xc->regs.intRegFile[i]);
     }
 
     // Then loop through the floating point registers.
     for (int i = 0; i < AlphaISA::NumFloatRegs; ++i)
     {
-        renamed_reg = renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
-        regFile.setFloatRegDouble(renamed_reg, xc->regs.floatRegFile.d[i]);
-        regFile.setFloatRegInt(renamed_reg, xc->regs.floatRegFile.q[i]);
+        renamed_reg = this->renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
+        this->regFile.setFloatRegDouble(renamed_reg,
+                                        this->xc->regs.floatRegFile.d[i]);
+        this->regFile.setFloatRegInt(renamed_reg,
+                                     this->xc->regs.floatRegFile.q[i]);
     }
 
     // Then loop through the misc registers.
-    regFile.miscRegs.fpcr = xc->regs.miscRegs.fpcr;
-    regFile.miscRegs.uniq = xc->regs.miscRegs.uniq;
-    regFile.miscRegs.lock_flag = xc->regs.miscRegs.lock_flag;
-    regFile.miscRegs.lock_addr = xc->regs.miscRegs.lock_addr;
+    this->regFile.miscRegs.fpcr = this->xc->regs.miscRegs.fpcr;
+    this->regFile.miscRegs.uniq = this->xc->regs.miscRegs.uniq;
+    this->regFile.miscRegs.lock_flag = this->xc->regs.miscRegs.lock_flag;
+    this->regFile.miscRegs.lock_addr = this->xc->regs.miscRegs.lock_addr;
 
     // Then finally set the PC and the next PC.
 //    regFile.pc = xc->regs.pc;
 //    regFile.npc = xc->regs.npc;
 
-    funcExeInst = xc->func_exe_inst;
+    this->funcExeInst = this->xc->func_exe_inst;
 }
 
 #ifdef FULL_SYSTEM
diff --git a/cpu/beta_cpu/bpred_unit.cc b/cpu/beta_cpu/bpred_unit.cc
index c4a79fbbe..c1b0f54b2 100644
--- a/cpu/beta_cpu/bpred_unit.cc
+++ b/cpu/beta_cpu/bpred_unit.cc
@@ -3,4 +3,4 @@
 #include "cpu/beta_cpu/alpha_impl.hh"
 #include "cpu/beta_cpu/alpha_dyn_inst.hh"
 
-template TwobitBPredUnit<AlphaSimpleImpl>;
+template class TwobitBPredUnit<AlphaSimpleImpl>;
diff --git a/cpu/beta_cpu/full_cpu.cc b/cpu/beta_cpu/full_cpu.cc
index d5228601c..04c74393b 100644
--- a/cpu/beta_cpu/full_cpu.cc
+++ b/cpu/beta_cpu/full_cpu.cc
@@ -15,22 +15,10 @@
 
 using namespace std;
 
-#ifdef FULL_SYSTEM
-BaseFullCPU::BaseFullCPU(Params &params)
-    : BaseCPU(params.name, params.numberOfThreads,
-              params.maxInstsAnyThread, params.maxInstsAllThreads,
-              params.maxLoadsAnyThread, params.maxLoadsAllThreads,
-              params._system, params.freq)
-{
-}
-#else
 BaseFullCPU::BaseFullCPU(Params &params)
-    : BaseCPU(params.name, params.numberOfThreads,
-              params.maxInstsAnyThread, params.maxInstsAllThreads,
-              params.maxLoadsAnyThread, params.maxLoadsAllThreads)
+    : BaseCPU(&params)
 {
 }
-#endif // FULL_SYSTEM
 
 template <class Impl>
 FullBetaCPU<Impl>::TickEvent::TickEvent(FullBetaCPU<Impl> *c)
@@ -515,6 +503,6 @@ FullBetaCPU<Impl>::wakeDependents(DynInstPtr &inst)
 }
 
 // Forward declaration of FullBetaCPU.
-template FullBetaCPU<AlphaSimpleImpl>;
+template class FullBetaCPU<AlphaSimpleImpl>;
 
 #endif // __SIMPLE_FULL_CPU_HH__
diff --git a/cpu/beta_cpu/full_cpu.hh b/cpu/beta_cpu/full_cpu.hh
index 19eb972d9..8ce32b7c7 100644
--- a/cpu/beta_cpu/full_cpu.hh
+++ b/cpu/beta_cpu/full_cpu.hh
@@ -27,27 +27,7 @@ class BaseFullCPU : public BaseCPU
 {
     //Stuff that's pretty ISA independent will go here.
   public:
-    class Params
-    {
-      public:
-#ifdef FULL_SYSTEM
-        std::string name;
-        int numberOfThreads;
-        Counter maxInstsAnyThread;
-        Counter maxInstsAllThreads;
-        Counter maxLoadsAnyThread;
-        Counter maxLoadsAllThreads;
-        System *_system;
-        Tick freq;
-#else
-        std::string name;
-        int numberOfThreads;
-        Counter maxInstsAnyThread;
-        Counter maxInstsAllThreads;
-        Counter maxLoadsAnyThread;
-        Counter maxLoadsAllThreads;
-#endif // FULL_SYSTEM
-    };
+    typedef BaseCPU::Params Params;
 
 #ifdef FULL_SYSTEM
     BaseFullCPU(Params &params);
diff --git a/cpu/beta_cpu/iew_impl.hh b/cpu/beta_cpu/iew_impl.hh
index b718e6aa0..1d072ab33 100644
--- a/cpu/beta_cpu/iew_impl.hh
+++ b/cpu/beta_cpu/iew_impl.hh
@@ -244,10 +244,10 @@ SimpleIEW<Impl, IQ>::squashDueToBranch(DynInstPtr &inst)
     // Also send PC update information back to prior stages.
     toCommit->squashedSeqNum = inst->seqNum;
     toCommit->mispredPC = inst->readPC();
-    toCommit->nextPC = inst->readCalcTarg();
+    toCommit->nextPC = inst->readNextPC();
     toCommit->branchMispredict = true;
     // Prediction was incorrect, so send back inverse.
-    toCommit->branchTaken = inst->readCalcTarg() !=
+    toCommit->branchTaken = inst->readNextPC() !=
         (inst->readPC() + sizeof(MachInst));
 }
 
@@ -265,7 +265,7 @@ SimpleIEW<Impl, IQ>::squashDueToMem(DynInstPtr &inst)
     toCommit->squash = true;
     // Also send PC update information back to prior stages.
     toCommit->squashedSeqNum = inst->seqNum;
-    toCommit->nextPC = inst->readCalcTarg();
+    toCommit->nextPC = inst->readNextPC();
 }
 
 template <class Impl, class IQ>
diff --git a/cpu/beta_cpu/inst_queue.cc b/cpu/beta_cpu/inst_queue.cc
index c4fd077bc..cd660ac79 100644
--- a/cpu/beta_cpu/inst_queue.cc
+++ b/cpu/beta_cpu/inst_queue.cc
@@ -4,7 +4,8 @@
 #include "cpu/beta_cpu/inst_queue_impl.hh"
 
 // Force instantiation of InstructionQueue.
-template InstructionQueue<AlphaSimpleImpl>;
+template class InstructionQueue<AlphaSimpleImpl>;
 
+template<>
 unsigned
 InstructionQueue<AlphaSimpleImpl>::DependencyEntry::mem_alloc_counter = 0;
diff --git a/cpu/beta_cpu/mem_dep_unit.cc b/cpu/beta_cpu/mem_dep_unit.cc
index 3175997f6..d8b5a80eb 100644
--- a/cpu/beta_cpu/mem_dep_unit.cc
+++ b/cpu/beta_cpu/mem_dep_unit.cc
@@ -6,4 +6,4 @@
 
 // Force instantation of memory dependency unit using store sets and
 // AlphaSimpleImpl.
-template MemDepUnit<StoreSet, AlphaSimpleImpl>;
+template class MemDepUnit<StoreSet, AlphaSimpleImpl>;
diff --git a/cpu/beta_cpu/ras.cc b/cpu/beta_cpu/ras.cc
index ca05f5a0d..23ca45b3a 100644
--- a/cpu/beta_cpu/ras.cc
+++ b/cpu/beta_cpu/ras.cc
@@ -4,7 +4,10 @@ ReturnAddrStack::ReturnAddrStack(unsigned _numEntries)
     : numEntries(_numEntries), usedEntries(0),
       tos(0)
 {
-    addrStack = new Addr[numEntries](0);
+    addrStack = new Addr[numEntries];
+
+    for (int i = 0; i < numEntries; ++i)
+        addrStack[i] = 0;
 }
 
 void
diff --git a/cpu/beta_cpu/rename_map.cc b/cpu/beta_cpu/rename_map.cc
index 1301202f2..45b8084de 100644
--- a/cpu/beta_cpu/rename_map.cc
+++ b/cpu/beta_cpu/rename_map.cc
@@ -1,6 +1,10 @@
 
+#include <vector>
+
 #include "cpu/beta_cpu/rename_map.hh"
 
+using namespace std;
+
 // Todo: Consider making functions inline.  Avoid having things that are
 // using the zero register or misc registers from adding on the registers
 // to the free list.  Possibly remove the direct communication between
diff --git a/cpu/beta_cpu/rename_map.hh b/cpu/beta_cpu/rename_map.hh
index 44a7eefb1..198cfc536 100644
--- a/cpu/beta_cpu/rename_map.hh
+++ b/cpu/beta_cpu/rename_map.hh
@@ -64,8 +64,8 @@ class SimpleRenameMap
 
     void setEntry(RegIndex arch_reg, PhysRegIndex renamed_reg);
 
-    void squash(vector<RegIndex> freed_regs,
-                vector<UnmapInfo> unmaps);
+    void squash(std::vector<RegIndex> freed_regs,
+                std::vector<UnmapInfo> unmaps);
 
     int numFreeEntries();
 
diff --git a/cpu/beta_cpu/rob.cc b/cpu/beta_cpu/rob.cc
index 611cca0ba..ad45c022f 100644
--- a/cpu/beta_cpu/rob.cc
+++ b/cpu/beta_cpu/rob.cc
@@ -4,4 +4,4 @@
 #include "cpu/beta_cpu/rob_impl.hh"
 
 // Force instantiation of InstructionQueue.
-template ROB<AlphaSimpleImpl>;
+template class ROB<AlphaSimpleImpl>;
diff --git a/cpu/beta_cpu/sat_counter.cc b/cpu/beta_cpu/sat_counter.cc
new file mode 100644
index 000000000..da095c3e1
--- /dev/null
+++ b/cpu/beta_cpu/sat_counter.cc
@@ -0,0 +1,43 @@
+#include "base/misc.hh"
+#include "cpu/beta_cpu/sat_counter.hh"
+
+SatCounter::SatCounter()
+    : maxVal(0), counter(0)
+{
+}
+
+SatCounter::SatCounter(unsigned bits)
+    : maxVal((1 << bits) - 1), counter(0)
+{
+}
+
+SatCounter::SatCounter(unsigned bits, unsigned initial_val)
+    : maxVal((1 << bits) - 1), counter(initial_val)
+{
+    // Check to make sure initial value doesn't exceed the max counter value.
+    if (initial_val > maxVal) {
+        panic("BP: Initial counter value exceeds max size.");
+    }
+}
+
+void
+SatCounter::setBits(unsigned bits)
+{
+    maxVal = (1 << bits) - 1;
+}
+
+void
+SatCounter::increment()
+{
+    if(counter < maxVal) {
+        ++counter;
+    }
+}
+
+void
+SatCounter::decrement()
+{
+    if(counter > 0) {
+        --counter;
+    }
+}
diff --git a/cpu/beta_cpu/sat_counter.hh b/cpu/beta_cpu/sat_counter.hh
new file mode 100644
index 000000000..e0f23e13e
--- /dev/null
+++ b/cpu/beta_cpu/sat_counter.hh
@@ -0,0 +1,62 @@
+#ifndef __CPU_BETA_CPU_SAT_COUNTER_HH__
+#define __CPU_BETA_CPU_SAT_COUNTER_HH__
+
+#include <stdint.h>
+
+/**
+ * Private counter class for the internal saturating counters.
+ * Implements an n bit saturating counter and provides methods to
+ * increment, decrement, and read it.
+ * @todo Consider making this something that more closely mimics a
+ * built in class so you can use ++ or --.
+ */
+class SatCounter
+{
+  public:
+    /**
+     * Constructor for the counter.
+     */
+    SatCounter();
+
+    /**
+     * Constructor for the counter.
+     * @param bits How many bits the counter will have.
+     */
+    SatCounter(unsigned bits);
+
+    /**
+     * Constructor for the counter.
+     * @param bits How many bits the counter will have.
+     * @param initial_val Starting value for each counter.
+     */
+    SatCounter(unsigned bits, unsigned initial_val);
+
+    /**
+     * Sets the number of bits.
+     */
+    void setBits(unsigned bits);
+
+    /**
+     * Increments the counter's current value.
+     */
+    void increment();
+
+    /**
+     * Decrements the counter's current value.
+     */
+    void decrement();
+
+    /**
+     * Read the counter's value.
+     */
+    const uint8_t read() const
+    {
+        return counter;
+    }
+
+  private:
+    uint8_t maxVal;
+    uint8_t counter;
+};
+
+#endif // __CPU_BETA_CPU_SAT_COUNTER_HH__
diff --git a/cpu/beta_cpu/tournament_pred.cc b/cpu/beta_cpu/tournament_pred.cc
index 53a11326a..5a22278eb 100644
--- a/cpu/beta_cpu/tournament_pred.cc
+++ b/cpu/beta_cpu/tournament_pred.cc
@@ -1,35 +1,5 @@
 #include "cpu/beta_cpu/tournament_pred.hh"
 
-TournamentBP::SatCounter::SatCounter(unsigned bits)
-    : maxVal((1 << bits) - 1), counter(0)
-{
-}
-
-TournamentBP::SatCounter::SatCounter(unsigned bits, unsigned initial_val)
-    : maxVal((1 << bits) - 1), counter(initial_val)
-{
-    // Check to make sure initial value doesn't exceed the max counter value.
-    if (initial_val > maxVal) {
-        panic("BP: Initial counter value exceeds max size.");
-    }
-}
-
-void
-TournamentBP::SatCounter::increment()
-{
-    if (counter < maxVal) {
-        ++counter;
-    }
-}
-
-void
-TournamentBP::SatCounter::decrement()
-{
-    if (counter > 0) {
-        --counter;
-    }
-}
-
 TournamentBP::TournamentBP(unsigned _local_predictor_size,
                            unsigned _local_ctr_bits,
                            unsigned _local_history_table_size,
@@ -54,21 +24,36 @@ TournamentBP::TournamentBP(unsigned _local_predictor_size,
     //Should do checks here to make sure sizes are correct (powers of 2)
 
     //Setup the array of counters for the local predictor
-    local_ctrs = new SatCounter[local_predictor_size](local_ctr_bits);
+    local_ctrs = new SatCounter[local_predictor_size];
+
+    for (int i = 0; i < local_predictor_size; ++i)
+        local_ctrs[i].setBits(local_ctr_bits);
+
     //Setup the history table for the local table
-    local_history_table = new unsigned[local_history_table_size](0);
+    local_history_table = new unsigned[local_history_table_size];
+
+    for (int i = 0; i < local_history_table_size; ++i)
+        local_history_table[i] = 0;
+
     // Setup the local history mask
     localHistoryMask = (1 << local_history_bits) - 1;
 
     //Setup the array of counters for the global predictor
-    global_ctrs = new SatCounter[global_predictor_size](global_ctr_bits);
+    global_ctrs = new SatCounter[global_predictor_size];
+
+    for (int i = 0; i < global_predictor_size; ++i)
+        global_ctrs[i].setBits(global_ctr_bits);
+
     //Clear the global history
     global_history = 0;
     // Setup the global history mask
     globalHistoryMask = (1 << global_history_bits) - 1;
 
     //Setup the array of counters for the choice predictor
-    choice_ctrs = new SatCounter[choice_predictor_size](choice_ctr_bits);
+    choice_ctrs = new SatCounter[choice_predictor_size];
+
+    for (int i = 0; i < choice_predictor_size; ++i)
+        choice_ctrs[i].setBits(choice_ctr_bits);
 
     threshold = (1 << (local_ctr_bits - 1)) - 1;
     threshold = threshold / 2;
diff --git a/cpu/beta_cpu/tournament_pred.hh b/cpu/beta_cpu/tournament_pred.hh
index bf87d753b..1512abc78 100644
--- a/cpu/beta_cpu/tournament_pred.hh
+++ b/cpu/beta_cpu/tournament_pred.hh
@@ -1,8 +1,9 @@
-#ifndef __TOURNAMENT_PRED_HH__
-#define __TOURNAMENT_PRED_HH__
+#ifndef __CPU_BETA_CPU_TOURNAMENT_PRED_HH__
+#define __CPU_BETA_CPU_TOURNAMENT_PRED_HH__
 
 // For Addr type.
 #include "arch/alpha/isa_traits.hh"
+#include "cpu/beta_cpu/sat_counter.hh"
 
 class TournamentBP
 {
@@ -48,52 +49,6 @@ class TournamentBP
 
     inline void updateHistoriesNotTaken(unsigned local_history_idx);
 
-    /**
-     * Private counter class for the internal saturating counters.
-     * Implements an n bit saturating counter and provides methods to
-     * increment, decrement, and read it.
-     * @todo Consider making this something that more closely mimics a
-     * built in class so you can use ++ or --.
-     */
-    class SatCounter
-    {
-      public:
-        /**
-         * Constructor for the counter.
-         * @param bits How many bits the counter will have.
-         */
-        SatCounter(unsigned bits);
-
-        /**
-         * Constructor for the counter.
-         * @param bits How many bits the counter will have.
-         * @param initial_val Starting value for each counter.
-         */
-        SatCounter(unsigned bits, unsigned initial_val);
-
-        /**
-         * Increments the counter's current value.
-         */
-        void increment();
-
-        /**
-         * Decrements the counter's current value.
-         */
-        void decrement();
-
-        /**
-         * Read the counter's value.
-         */
-        uint8_t read()
-        {
-            return counter;
-        }
-
-      private:
-        uint8_t maxVal;
-        uint8_t counter;
-    };
-
     /** Local counters. */
     SatCounter *local_ctrs;
 
@@ -157,4 +112,4 @@ class TournamentBP
     unsigned threshold;
 };
 
-#endif // __TOURNAMENT_PRED_HH__
+#endif // __CPU_BETA_CPU_TOURNAMENT_PRED_HH__