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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-03-10 16:26:31 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-03-10 16:26:31 -0500 |
| commit | 68d7382cf37a3f765a7cc650fcef04fb1548fa39 (patch) | |
| tree | df11fec7d7434ed60804bf367904215dfb45dfcc /cpu/cpu_exec_context.hh | |
| parent | e3d96aa889680469be44bb9cd59d3db837cb4dc4 (diff) | |
| download | gem5-68d7382cf37a3f765a7cc650fcef04fb1548fa39.tar.xz | |
Eliminated TARGET_ALPHA, since THE_ISA provides the same function.
--HG--
extra : convert_revision : eb173a553b0782891e8b4a8e227bfb647390883a
Diffstat (limited to 'cpu/cpu_exec_context.hh')
| -rw-r--r-- | cpu/cpu_exec_context.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh index 6f725d1e4..6cc586467 100644 --- a/cpu/cpu_exec_context.hh +++ b/cpu/cpu_exec_context.hh @@ -284,7 +284,7 @@ class CPUExecContext template <class T> Fault read(CpuRequestPtr &req, T &data) { -#if FULL_SYSTEM && defined(TARGET_ALPHA) +#if FULL_SYSTEM && THE_ISA == ALPHA_ISA if (req->flags & LOCKED) { req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr); req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true); @@ -300,7 +300,7 @@ class CPUExecContext template <class T> Fault write(CpuRequestPtr &req, T &data) { -#if FULL_SYSTEM && defined(TARGET_ALPHA) +#if FULL_SYSTEM && THE_ISA == ALPHA_ISA ExecContext *xc; // If this is a store conditional, act appropriately |